公开(公告)号：US20240395615A1

公开(公告)日：2024-11-28

申请号：US18631548

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokwon Kim ,  Bongjin Kuh ,  Sukhoon Kim ,  Jiho Park ,  Sanghyeok Yu ,  Yongho Ha ,  Musarrat Hasan

IPC: H01L21/768 ,  C23C16/34 ,  C23C16/505

Abstract: A method of manufacturing a semiconductor device includes forming a substrate including a structure having a first region and a contact hole exposing the first region, loading the substrate into a process chamber, repeatedly performing two or more times, a deposition process that includes repeatedly applying radio frequency (RF) plasma power to a process gas for a first time duration and not applying the RF plasma power to the process gas for a second time duration, and a soak process that does not use plasma, at a metal-semiconductor compound formation temperature or higher, within the process chamber, and thereby forming a metal-semiconductor compound layer on the first region, a sidewall material layer on a sidewall of the contact hole, and an upper material layer on the structure, performing a removal process of removing at least a portion of the sidewall material layer in the process chamber, and unloading the substrate from the process chamber after performing the removal process.

公开(公告)号：US20240371717A1

公开(公告)日：2024-11-07

申请号：US18409221

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donggon Yoo ,  Sunjung Lee ,  Jeongwon Hwang ,  Myung-Ho Kong ,  Yongho Ha

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a mold layer defining a trench and a conductive structure disposed on the trench. The conductive structure includes a conductive layer and a liner, and the conductive layer includes upper and lower portions. The liner includes a base portion and a sidewall portion on the base portion, and the upper portion of the conductive layer is disposed at a level higher than the sidewall portion of the liner. The sidewall portion of the liner is interposed between the lower portion of the conductive layer and the mold layer, and a top surface of the base portion of the liner is in contact with a bottom surface of the lower portion of the conductive layer. A width of the sidewall portion of the liner may decrease as a level increases.

公开(公告)号：US11901356B2

公开(公告)日：2024-02-13

申请号：US16817069

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungha Oh ,  Pil-Kyu Kang ,  Kughwan Kim ,  Weonhong Kim ,  Yuichiro Sasaki ,  Sang Woo Lee ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L27/06 ,  H01L23/48 ,  H10B41/60 ,  H10B43/20 ,  H10B63/00

CPC classification number: H01L27/0688 ,  H01L23/481 ,  H10B41/60 ,  H10B43/20 ,  H10B63/30 ,  H10B63/84

Abstract: A three-dimensional semiconductor device includes a lower substrate, a plurality of lower transistors disposed on the lower substrate, an upper substrate disposed on the lower transistors, a plurality of lower conductive lines disposed between the lower transistors and the upper substrate, and a plurality of upper transistors disposed on the upper substrate. At least one of the lower transistors is connected to a corresponding one of the lower conductive lines. Each of the upper transistors includes an upper gate electrode disposed on the upper substrate, a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode, and a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode. The upper gate electrode includes silicon germanium (SiGe).

公开(公告)号：US11610838B2

公开(公告)日：2023-03-21

申请号：US17367773

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichiro Sasaki ,  Sungkeun Lim ,  Pil-Kyu Kang ,  Weonhong Kim ,  Seungha Oh ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

公开(公告)号：US11177286B2

公开(公告)日：2021-11-16

申请号：US16807410

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/762 ,  H01L27/02

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US11121080B2

公开(公告)日：2021-09-14

申请号：US16809788

申请日：2020-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichiro Sasaki ,  Sungkeun Lim ,  Pil-Kyu Kang ,  Weonhong Kim ,  Seungha Oh ,  Yongho Ha ,  Sangjin Hyun

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

公开(公告)号：US20240429303A1

公开(公告)日：2024-12-26

申请号：US18658176

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donggon Yoo ,  Eunhyea Ko ,  Sunjung Lee ,  Yongho Ha ,  Jeongwon Hwang

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An integrated circuit device includes a substrate, a fin-type active region extending in a first horizontal direction on a first surface of the substrate, a source/drain region on the fin-type active region, an active contact on the source/drain region and electrically connected to the source/drain region, a wiring line extending at a vertical level higher than the source/drain region, a via contact penetrating an insulating layer on the source/drain region and serving as a medium of electrical connection between the active contact and the wiring line, and an adhesive layer between the wiring line and the insulating layer and contacting the wiring line, wherein the via contact includes a top via contact and a bottom via contact, the top via contact includes a metal different from a metal included in the bottom via contact, and the wiring line and the top via contact are in direct contact with each other.

公开(公告)号：US11728347B2

公开(公告)日：2023-08-15

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/76224 ,  H01L27/0203 ,  H01L27/02 ,  H01L29/78

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US20230165012A1

公开(公告)日：2023-05-25

申请号：US18049366

申请日：2022-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gabjin Nam ,  Bongjin Kuh ,  Musarrat Hasan ,  Geonju Park ,  Yongho Ha

IPC: H01L27/1159

CPC classification number: H01L27/1159

Abstract: A ferroelectric memory device according to the inventive concept includes a substrate having source/drain regions, an interface layer on the substrate, a high dielectric layer on the interface layer, a ferroelectric layer on the high dielectric layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures.