公开(公告)号：US11023396B2

公开(公告)日：2021-06-01

申请号：US16519487

申请日：2019-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

公开(公告)号：US20200241886A1

公开(公告)日：2020-07-30

申请号：US16599358

申请日：2019-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cholmin Kim ,  Jiyong Lee ,  Jongmin Park ,  Deokho Seo ,  Kwanghee Lee

IPC: G06F9/4401 ,  G06F21/60 ,  G06F13/16 ,  G06Q20/06

Abstract: A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

公开(公告)号：US11436022B2

公开(公告)日：2022-09-06

申请号：US16599358

申请日：2019-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cholmin Kim ,  Jiyong Lee ,  Jongmin Park ,  Deokho Seo ,  Kwanghee Lee

IPC: G06F13/00 ,  G06F9/4401 ,  G06Q20/06 ,  G06F13/16 ,  G06F21/60

Abstract: A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

公开(公告)号：US09934830B2

公开(公告)日：2018-04-03

申请号：US15298335

申请日：2016-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin Park ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Sungup Moon ,  Kyoyeon Won

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/02

CPC classification number: G11C7/1012 ,  G11C7/02 ,  G11C7/22

Abstract: In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.

公开(公告)号：US20250105998A1

公开(公告)日：2025-03-27

申请号：US18894658

申请日：2024-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwook Burm ,  Jongmin Park

IPC: H04L7/00 ,  H03K3/037

Abstract: An integrated circuit includes a phase shifted data generation circuit, a synchronization circuit, and a control signal generation circuit configured to generate a reference clock control signal that controls at least one of a phase and a frequency of the reference clock signal by performing a logical operation on a plurality of received synchronization data.

公开(公告)号：US11005462B1

公开(公告)日：2021-05-11

申请号：US16927586

申请日：2020-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin Park

IPC: H03K5/12 ,  H03K19/0175 ,  H03K5/1252

Abstract: An interface device, including a plurality of interface circuits, wherein each interface circuit of the plurality of interface circuits includes a first switching element connected in series to a second switching element, and a first capacitor and a second capacitor connected to an output terminal to which the first switching element and the second switching element are connected; and a controller configured to determine a plurality of output signals corresponding to the plurality of interface circuits by controlling the first switching element and the second switching element, and configured to adjust a slew rate of the plurality of output signals by charging and discharging the first capacitor and the second capacitor.

公开(公告)号：US10366021B2

公开(公告)日：2019-07-30

申请号：US15390063

申请日：2016-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.