公开(公告)号：US12236104B2

公开(公告)日：2025-02-25

申请号：US17889117

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jeong Kim ,  Tae-Kyeong Ko ,  Nam Hyung Kim ,  Do-Han Kim ,  Deokho Seo ,  Ho-Young Lee ,  Insu Choi

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

公开(公告)号：US12141478B2

公开(公告)日：2024-11-12

申请号：US17932734

申请日：2022-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deokho Seo ,  Taekyeong Ko ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Hoyoung Lee ,  Insu Choi

IPC: G06F3/06 ,  H03M13/00 ,  H03M13/11

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

公开(公告)号：US11487613B2

公开(公告)日：2022-11-01

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Minsu Kim ,  Deokho Seo ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/30

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

公开(公告)号：US11436022B2

公开(公告)日：2022-09-06

申请号：US16599358

申请日：2019-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cholmin Kim ,  Jiyong Lee ,  Jongmin Park ,  Deokho Seo ,  Kwanghee Lee

IPC: G06F13/00 ,  G06F9/4401 ,  G06Q20/06 ,  G06F13/16 ,  G06F21/60

Abstract: A semiconductor memory device for a hash solution includes a hashing logic block including a plurality of hashing logics configured to perform a hash function, a memory cell block including a plurality of memory cells, and an input/output (I/O) control structure configured to change a data interface between the hashing logic block and the memory cell block based on a characteristic of the hash function to be performed.

公开(公告)号：US11721408B2

公开(公告)日：2023-08-08

申请号：US17388238

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daejeong Kim ,  Namhyung Kim ,  Dohan Kim ,  Deokho Seo ,  Wonjae Shin ,  Insu Choi

IPC: G01R31/28 ,  G11C29/42 ,  G11C29/50 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G11C29/50004 ,  G11C2029/5004

Abstract: A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

公开(公告)号：US11610624B2

公开(公告)日：2023-03-21

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

公开(公告)号：US20220215871A1

公开(公告)日：2022-07-07

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11887692B2

公开(公告)日：2024-01-30

申请号：US17535861

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Insu Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1009 ,  G11C7/109 ,  G11C7/1063 ,  G11C8/18

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

公开(公告)号：US11670355B2

公开(公告)日：2023-06-06

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40618

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11321177B2

公开(公告)日：2022-05-03

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C11/4091 ,  G11C11/408

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.