公开(公告)号：US20190158116A1

公开(公告)日：2019-05-23

申请号：US16024017

申请日：2018-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Kyu LEE ,  Jae-Hong KIM ,  Ki-Jun LEE ,  Jun-Jin KONG ,  Hong-Rak SON ,  Se-Jin LIM ,  Young-Jun HWANG

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00

Abstract: A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

公开(公告)号：US20140115424A1

公开(公告)日：2014-04-24

申请号：US14052834

申请日：2013-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Seuk YOO ,  Jun-Jin KONG ,  Chang-Kyu SEOL ,  Hong-Rak SON ,  Young-Geon YOO

IPC: G06F12/00 ,  G06F11/10 ,  G06F12/02

CPC classification number: G06F12/00 ,  G06F11/10 ,  G06F11/1048 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5648

Abstract: Provided is a method of operating a memory system. The method includes programming first bit data into multiple memory cells; identifying target memory cells that are in a first state and have threshold voltages equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating multiple third bit data by performing a first process on the second bit data; and selecting third bit data of the calculated multiple third bit data that changes a largest number of target memory cells from the first state to a second state when the memory cells are programmed with each of the multiple third bit data, respectively. The selected third bit data is programmed into the memory cells.

Abstract translation: 提供了一种操作存储器系统的方法。 该方法包括将第一位数据编程到多个存储器单元中; 识别处于第一状态并且具有等于或大于来自由第一位数据编程的存储器单元的第一电压的阈值电压的目标存储器单元; 接收要编程到存储器单元中的第二位数据; 通过对所述第二位数据执行第一处理来计算多个第三位数据; 以及当所述存储器单元分别被所述多个第三位数据中的每一个编程时，选择将所述最大数目的目标存储单元从所述第一状态改变到第二状态的所计算的多个第三位数据的第三位数据。 所选择的第三位数据被编程到存储器单元中。

公开(公告)号：US20170024278A1

公开(公告)日：2017-01-26

申请号：US14808505

申请日：2015-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moshe TWITTO ,  Jun-Jin KONG

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory controller of a memory system, the memory system including the memory controller and a memory device, includes a processor configured to receive write data an control the memory controller; and an encoder, the processor being configured to, receive write data, read previously programmed data from a first memory page of a memory cell array of the memory device, and control the encoder to generate encoded data by encoding the write data using stuck bit code (SBC), based on the read previously programmed data, the previously programmed data being data that has been programmed into the first memory page of the memory cell array and has not been erased; the processor being configured to write the encoded data to the first memory page without erasing the first memory page.

Abstract translation: 存储器系统的存储器控​​制器，包括存储器控制器和存储器件的存储器系统，包括：处理器，被配置为接收写入数据，控制存储器控制器; 以及编码器，所述处理器被配置为接收写入数据，从所述存储器件的存储器单元阵列的第一存储器页面读取先前编程的数据，并且通过使用卡位位代码对写入数据进行编码来控制编码器生成编码数据 （SBC），基于读取的先前编程的数据，先前编程的数据是已被编程到存储器单元阵列的第一存储器页面中并且尚未被擦除的数据; 处理器被配置为将编码数据写入第一存储器页，而不擦除第一存储器页。