公开(公告)号：US20230178518A1

公开(公告)日：2023-06-08

申请号：US17889053

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raehyung DO ,  Seunghyun GO ,  Jungsik LEE ,  Jongho LEE ,  Younghun CHEONG ,  Cheolsoo HAN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/4911 ,  H01L2224/49421 ,  H01L2224/49422 ,  H01L2224/49426 ,  H01L2225/06562 ,  H01L2224/49052 ,  H01L2224/48091 ,  H01L2224/05624 ,  H01L24/05 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85484 ,  H01L2224/85466 ,  H01L24/85 ,  H01L2224/45144 ,  H01L24/45

Abstract: A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.