公开(公告)号：US20230411354A1

公开(公告)日：2023-12-21

申请号：US18096859

申请日：2023-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chihong SHIN ,  Raehyung DO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L24/06 ,  H01L23/49838 ,  H01L23/3121 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2224/48227 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2224/49096 ,  H01L2224/49051 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/04042 ,  H01L2224/06135

Abstract: A semiconductor package includes a package substrate having substrate pads disposed in a first direction on one surface, a semiconductor chip having chip pads disposed in the first direction, and bonding wires connecting the chip pads and the substrate pads. The bonding wires include first and second bonding wires alternately connected to the substrate pads respectively, in the first direction, the first bonding wires are connected to the substrate pads at a first angle less than a right angle with respect to a direction of the semiconductor chip, the second bonding wires are connected to the substrate pads at a second angle less than the first angle with respect to the direction of the semiconductor chip and a position at which the first bonding wires contact the substrate pads is closer to the semiconductor chip than a position at which the second bonding wires contact the substrate pads is to the semiconductor chip.

公开(公告)号：US20230178518A1

公开(公告)日：2023-06-08

申请号：US17889053

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raehyung DO ,  Seunghyun GO ,  Jungsik LEE ,  Jongho LEE ,  Younghun CHEONG ,  Cheolsoo HAN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/4911 ,  H01L2224/49421 ,  H01L2224/49422 ,  H01L2224/49426 ,  H01L2225/06562 ,  H01L2224/49052 ,  H01L2224/48091 ,  H01L2224/05624 ,  H01L24/05 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85484 ,  H01L2224/85466 ,  H01L24/85 ,  H01L2224/45144 ,  H01L24/45

Abstract: A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.

公开(公告)号：US20220093673A1

公开(公告)日：2022-03-24

申请号：US17306267

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raehyung DO ,  Jongho LEE ,  Kundae YEOM

IPC: H01L27/146 ,  H05K3/40 ,  H05K1/03 ,  H04N5/374

Abstract: An image sensor package includes a circuit board, an image sensor chip on the circuit board, a stack bump structure on the image sensor chip, a bonding wire connecting the circuit board to the stack bump structure, a dam element on the image sensor chip and covering both the stack bump structure and the bonding wire, and a molding element contacting the dam element on the circuit board and covering both the image sensor chip and the bonding wire.