METHOD AND DEVICE TO ALIGN PHASES OF CLOCK SIGNALS

    公开(公告)号:US20170250695A1

    公开(公告)日:2017-08-31

    申请号:US15443060

    申请日:2017-02-27

    Abstract: In a method and device to align phases of a first clock signal and a second clock signal, include a phase detector, a delay generator, and a controller. The phase detector is configured to generate a preceding signal and a succeeding signal with respect to the first clock signal to detect a relationship between phases of the first clock signal and the second clock signal. The delay generator is configured to delay the first clock signal when the second clock signal falls behind the succeeding signal with respect to the first clock signal. The controller is configured to determine whether the phases of the first clock signal and the second clock signal are aligned with each other according to the relationship detected by the phase detector.

    Computing apparatuses and methods of processing operations thereof

    公开(公告)号:US10990589B2

    公开(公告)日:2021-04-27

    申请号:US15672800

    申请日:2017-08-09

    Abstract: A computing apparatus may process an operation. The computing apparatus may output information regarding an aggregation operation and an operand corresponding to a variable stored in a memory, store information regarding an operator and the aggregation operands regarding the aggregation operation, perform a first partial operation with respect to the aggregation operands and store a result value of the first partial operation, and process the aggregation operation based on storing the variable, performing a second partial operation with respect to the result value of the first partial operation stored in the cache and the operand corresponding to the variable, and storing a result value of the second partial operation.

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