公开(公告)号：US20200349093A1

公开(公告)日：2020-11-05

申请号：US16569657

申请日：2019-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G06F13/16 ,  G06F12/06

Abstract: A high-bandwidth memory (HBM) includes a memory and a controller. The controller receives a data write request from a processor external to the HBM and the controller stores an entry in the memory indicating at least one address of data of the data write request and generates an indication that a data bus is available for an operation during a cycle time of the data write request based on the data write request comprising sparse data or data-value similarity. Sparse data includes a predetermined percentage of data values equal to zero, and data-value similarity includes a predetermined amount of spatial value locality of the data values. The predetermined percentage of data values equal to zero of sparse data and the predetermined amount of spatial value locality of the special-value pattern are both based on a predetermined data granularity.

公开(公告)号：US20160173101A1

公开(公告)日：2016-06-16

申请号：US14838347

申请日：2015-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu GAO ,  Hongzhong ZHENG ,  Krishna T. MALLADI ,  Robert BRENNAN

IPC: H03K19/177 ,  H01L25/00 ,  H01L25/18

CPC classification number: H03K19/1776 ,  H01L25/18 ,  H01L25/50 ,  H01L2924/0002 ,  H03K19/17728 ,  H03K19/17736 ,  H01L2924/00

Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to store data in a random access fashion. The dies may also include a look-up table die comprising a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may be configured to perform a logic function. The reconfigurable look-up table may include a plurality of random access memory cells configured to store a look-up table to perform a logic function, and a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The look-up table stored in the plurality of memory cells may be configured to be dynamically altered via a memory write operation to the random access memory array.

Abstract translation: 根据一个一般方面，一种装置可以包括多个堆叠的集成电路管芯。 管芯可以包括被配置为以随机存取方式存储数据的存储单元管芯。 模具还可以包括查找表模具，其包括随机存取存储器阵列，其又包括可重新配置的查找表。 可重构查找表可以被配置为执行逻辑功能。 可配置查找表可以包括被配置为存储查询表以执行逻辑功能的多个随机存取存储器单元，以及配置成基于一组输入来激活一行或多行存储器单元的本地行解码器 信号。 存储在多个存储器单元中的查找表可以被配置为通过存储器写入操作来动态地改变到随机存取存储器阵列。

公开(公告)号：US20240193111A1

公开(公告)日：2024-06-13

申请号：US18444619

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

IPC: G06F13/28 ,  G06F9/445 ,  G06F9/48 ,  G06F15/76

CPC classification number: G06F13/28 ,  G06F9/445 ,  G06F9/4806 ,  G06F2015/768

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

公开(公告)号：US20230147472A1

公开(公告)日：2023-05-11

申请号：US17670044

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shiyu LI ,  Krishna T. MALLADI ,  Andrew CHANG ,  Yang Seok KI

IPC: G06T1/60 ,  G06T1/20 ,  G06F13/40 ,  G06F16/22

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F13/4022 ,  G06F16/2237 ,  G06F16/2282

Abstract: A system and method for training a neural network. In some embodiments, the system includes: a graphics processing unit cluster; and a computational storage cluster connected to the graphics processing unit cluster by a cache-coherent system interconnect. The graphics processing unit cluster may include one or more graphics processing units. The computational storage cluster may include one or more computational storage devices. A first computational storage device of the one or more computational storage devices may be configured to (i) store an embedding table, (ii) receive an index vector including a first index and a second index; and (iii) calculate an embedded vector based on: a first row of the embedding table, corresponding to the first index, and a second row of the embedding table, corresponding to the second index.

公开(公告)号：US20200042477A1

公开(公告)日：2020-02-06

申请号：US16595452

申请日：2019-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

IPC: G06F13/28 ,  G06F9/445 ,  G06F9/48

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

公开(公告)号：US20250028642A1

公开(公告)日：2025-01-23

申请号：US18905936

申请日：2024-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Andrew Z. CHANG ,  Ehsan NAJAFABADI

IPC: G06F12/0817

Abstract: A coherent memory system. In some embodiments, the coherent memory system includes a first memory device. The first memory device may include a cache coherent controller; a volatile memory controller; a volatile memory; a nonvolatile memory controller; and a nonvolatile memory. The first memory device may be configured to receive a quality of service requirement and to selectively enable a first feature in response to the quality of service requirement.

公开(公告)号：US20210141735A1

公开(公告)日：2021-05-13

申请号：US17156362

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Krishna T. MALLADI ,  Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG

IPC: G06F12/0879 ,  G11C11/417

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

公开(公告)号：US20210117103A1

公开(公告)日：2021-04-22

申请号：US17133987

申请日：2020-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F15/78 ,  G06F13/42

Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit receives a first command from the host device and converts the received first command to a processing-in-memory (PIM) command that is sent to the HBM device through the second interface. A time between when the first command is received from the host device and when the HBM system is ready to receive another command from the host device is deterministic. The logic circuit further receives a fourth command and a fifth command from the host device. The fifth command requests time-estimate information relating to a time between when the fifth command is received and when the HBM system is ready to receive another command from the host device. The time-estimate information includes a deterministic period of time and an estimated period of time for a non-deterministic period of time.

公开(公告)号：US20190079886A1

公开(公告)日：2019-03-14

申请号：US15825047

申请日：2017-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

IPC: G06F13/28 ,  G06F9/48 ,  G06F9/445

CPC classification number: G06F13/28 ,  G06F9/445 ,  G06F9/4806 ,  G06F2015/768

Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.

公开(公告)号：US20230281128A1

公开(公告)日：2023-09-07

申请号：US17834896

申请日：2022-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wenqin HUANGFU ,  Krishna T. MALLADI ,  Andrew CHANG

IPC: G06F12/0817 ,  G06F12/0831 ,  G06F9/52

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F9/52

Abstract: A memory system is disclosed. The memory system may include a first cache-coherent interconnect memory module and a second cache-coherent interconnect memory module. A cache-coherent interconnect switch may connect the first cache-coherent interconnect memory module, the second cache-coherent interconnect memory module, and a processor. A processing element may process a data stored on at least one of the first cache-coherent interconnect memory module and the second cache-coherent interconnect memory module.