公开(公告)号：US20210081278A1

公开(公告)日：2021-03-18

申请号：US17105205

申请日：2020-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun SEO ,  Kwang-Il PARK ,  Seung-Jun BAE ,  Sang-Uhn CHA

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093 ,  H01L25/065

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

公开(公告)号：US20190250985A1

公开(公告)日：2019-08-15

申请号：US16228560

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun SEO ,  Kwang-Il PARK ,  Seung-Jun BAE ,  Sang-Uhn CHA

IPC: G06F11/10 ,  G11C29/52 ,  H01L25/065 ,  G11C11/4093

CPC classification number: G06F11/1068 ,  G11C11/4093 ,  G11C29/52 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

公开(公告)号：US20150134895A1

公开(公告)日：2015-05-14

申请号：US14465995

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Kwang-Il PARK ,  Hak-Soo YU

IPC: G11C14/00 ,  G11C11/00

CPC classification number: G11C14/0018 ,  G11C11/40 ,  G11C29/702 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Abstract translation: 半导体存储器件可以包括包括多个存储器单元的单元阵列，每个存储器单元连接到字线和位线，单元阵列被划分成多个块，每个块包括多个字线，多个字线 的至少包括第一缺陷块的块; 非易失性存储电路，被配置为存储所述第一缺陷块的地址信息，并将所述地址信息输出到外部设备; 以及熔丝电路，被配置为切断第一有缺陷块的字线的激活。

公开(公告)号：US20170062038A1

公开(公告)日：2017-03-02

申请号：US15065211

申请日：2016-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-Yeon DOO ,  Tae-Young OH ,  Kwang-Il PARK

IPC: G11C11/406

CPC classification number: G06F13/1636 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40615

Abstract: A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells. The memory controller controls the semiconductor memory device. The memory controller applies an auto-refresh command to the semiconductor memory device at each refresh interval of the semiconductor memory device such that the semiconductor memory performs a refresh operation in a normal mode, and does not apply the auto-refresh command to the semiconductor memory device during a self-refresh interval in which the semiconductor memory performs a self-refresh operation. After the semiconductor memory device exits from the self-refresh interval, the memory controller adjusts an application of the auto-refresh command in the normal mode by reflecting information of the self-refresh interval.

Abstract translation: 存储器系统包括半导体存储器件和存储器控制器。 半导体存储器件包括多个动态存储单元。 存储器控制器控制半导体存储器件。 存储器控制器在半导体存储器件的每个刷新间隔处向半导体存储器件施加自动刷新命令，使得半导体存储器以正常模式执行刷新操作，并且不将自动刷新命令应用于半导体存储器 在自刷新间隔期间，半导体存储器执行自刷新操作。 在半导体存储器件退出自刷新间隔之后，存储器控制器通过反映自刷新间隔的信息来调整在正常模式下的自动刷新命令的应用。