公开(公告)号：US20190250985A1

公开(公告)日：2019-08-15

申请号：US16228560

申请日：2018-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun SEO ,  Kwang-Il PARK ,  Seung-Jun BAE ,  Sang-Uhn CHA

IPC: G06F11/10 ,  G11C29/52 ,  H01L25/065 ,  G11C11/4093

CPC classification number: G06F11/1068 ,  G11C11/4093 ,  G11C29/52 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

公开(公告)号：US20130100998A1

公开(公告)日：2013-04-25

申请号：US13714473

申请日：2012-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jun BAE ,  Seong-Jin JANG ,  Beom-Sig CHO

IPC: H04L7/10

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A method of communication to a semiconductor device includes: transmitting a sampling clock signal from a first semiconductor device to a second semiconductor device; transmitting a training signal from the first semiconductor device to the second semiconductor device while transmitting of the sampling clock signal, the training signal comprising plural test patterns sent sequentially to the second semiconductor device, phases of at least some of the test patterns being adjusted to be different from each other during transmitting of the training signal; receiving first information from the second semiconductor device over a first signal line, the first signal line separate from a data bus connected between the first semiconductor device and the second semiconductor device; and transmitting a data signal over the data bus while transmitting the sampling clock signal, the data signal sent at a timing with respect to the sampling clock signal responsive to the received first information.

Abstract translation: 一种与半导体器件通信的方法包括：将采样时钟信号从第一半导体器件传输到第二半导体器件; 在将所述采样时钟信号发送的同时将训练信号从所述第一半导体器件传输到所述第二半导体器件，所述训练信号包括顺序发送到所述第二半导体器件的多个测试图案，所述至少一些所述测试图案的相位被调整为 在训练信号的发送期间彼此不同; 通过第一信号线从第二半导体器件接收第一信息，第一信号线与连接在第一半导体器件和第二半导体器件之间的数据总线分开; 并且在发送采样时钟信号的同时，通过数据总线发送数据信号，所述数据信号响应于所接收到的第一信息而相对于采样时钟信号在定时发送。

公开(公告)号：US20210081278A1

公开(公告)日：2021-03-18

申请号：US17105205

申请日：2020-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun SEO ,  Kwang-Il PARK ,  Seung-Jun BAE ,  Sang-Uhn CHA

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093 ,  H01L25/065

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

公开(公告)号：US20150213873A1

公开(公告)日：2015-07-30

申请号：US14558072

申请日：2014-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Yoon JOO ,  Seung-Jun BAE ,  Young-Soo SOHN ,  Ho-Sung SONG ,  Jeong-Don IHM

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  H03L7/089 ,  H03L7/087

CPC classification number: H03L7/087 ,  G11C7/222 ,  H03L7/07 ,  H03L7/083 ,  H03L7/0995

Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Abstract translation: 注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。 将DLL时钟作为VCO的注入时钟注入到VCO中。

公开(公告)号：US20140032826A1

公开(公告)日：2014-01-30

申请号：US13941359

申请日：2013-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-Jin LEE ,  Dae-Hyun KIM ,  Seung-Jun BAE ,  Young-Soo SOHN ,  Tae-Young OH

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F9/4403 ,  G11C11/40 ,  G11C11/4072 ,  G11C29/028 ,  G11C2029/4402

Abstract: A method of training a memory device included in a memory system is provided. The method includes testing memory core parameters for a memory core of the memory device during a booting-up sequence of the memory system; determining trimmed memory core parameters based on the test results; storing the determined trimmed memory core parameters; and applying the trimmed memory core parameter to the memory device during a normal operation of the memory device.

Abstract translation: 提供了一种训练包括在存储器系统中的存储器件的方法。 该方法包括在存储器系统的引导序列期间测试存储器件的存储器核心的存储器核心参数; 根据测试结果确定修剪内存核心参数; 存储所确定的修整的存储器核心参数; 以及在存储器件的正常操作期间将修整的存储器核心参数应用于存储器件。

公开(公告)号：US20150325274A1

公开(公告)日：2015-11-12

申请号：US14644339

申请日：2015-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong SHIM ,  Seung-Jun BAE ,  Won-Joo YUN

IPC: G11C7/10

CPC classification number: G11C7/1084 ,  G11C7/1054

Abstract: An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.

Abstract translation: 输入缓冲器包括第一缓冲器，反馈电路和第二缓冲电路。 反馈电路包括反馈电阻和反馈反馈器。 第一缓冲器可以被配置为基于输入信号将放大信号输出到第一缓冲器的输出节点。 连接到第一缓冲器的输出节点的反馈电路可以被配置为控制放大信号。 第二缓冲电路可以被配置为通过缓冲放大信号来输出缓冲器输出信号。 反馈电阻器可以从第一缓冲器的输出节点接收放大信号，并向反馈节点提供反馈信号。 反馈逆变器连接在反馈节点和输出节点之间。 反馈反相器可以被配置为基于反馈信号来控制放大信号。

公开(公告)号：US20140119140A1

公开(公告)日：2014-05-01

申请号：US14066193

申请日：2013-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Seok SEOL ,  Seung-Jun BAE ,  Ho-Sung SONG

IPC: H03K3/017 ,  G11C8/18 ,  G11C7/22

CPC classification number: G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03K5/1565

Abstract: A duty cycle corrector includes a sensing unit, a pad unit, a fuse unit, and a driver unit. The sensing unit generates at least one sensing signal based on the sensed duty cycle ratio of an output signal. The pad unit outputs at least one decision signal based on the at least one sensing signal. The fuse unit generates a duty cycle control signal based on at least one received fuse control signal. The driver unit adjusts a duty cycle ratio of an input signal to generate the output signal based on the duty cycle control signal. The driver unit adjusts the duty cycle ratio of the input signal by adjusting a pull-up strength or a pull-down strength of the input signal based on the duty cycle control signal.

Abstract translation: 占空比校正器包括感测单元，衬垫单元，保险丝单元和驱动单元。 感测单元基于感测到的输出信号的占空比来产生至少一个感测信号。 垫单元基于至少一个感测信号输出至少一个判定信号。 熔丝单元基于至少一个接收的熔丝控制信号产生占空比控制信号。 驱动单元根据占空比控制信号来调整输入信号的占空比，生成输出信号。 驱动器单元通过基于占空比控制信号调整输入信号的上拉强度或下拉强度来调整输入信号的占空比。

公开(公告)号：US20140089574A1

公开(公告)日：2014-03-27

申请号：US14018927

申请日：2013-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Dae-Hyun KIM ,  Seung-Jun BAE ,  Tae-young OH ,  Woo-jin LEE

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/1054 ,  G11C7/1063 ,  G11C7/1081 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2029/4402

Abstract: A semiconductor memory device storing memory characteristic information, a memory module including the semiconductor memory device, a memory system, and an operating method of the semiconductor memory device. The semiconductor memory device may include a cell array including a plurality of areas; a command decoder configured to decode a command and generate an internal command; and an information storage unit configured to store characteristic information of at least one of the plurality of areas. When a first command and a first row address accompanying the first command are received, characteristic information of an area corresponding to the first row address is provided to an outside.

Abstract translation: 存储存储特性信息的半导体存储器件，包括半导体存储器件的存储器模块，存储器系统以及半导体存储器件的操作方法。 半导体存储器件可以包括包括多个区域的单元阵列; 命令解码器，被配置为解码命令并产生内部命令; 以及信息存储单元，被配置为存储所述多个区域中的至少一个的特征信息。 当接收到伴随第一命令的第一命令和第一行地址时，向外部提供对应于第一行地址的区域的特征信息。

公开(公告)号：US20140266299A1

公开(公告)日：2014-09-18

申请号：US14202323

申请日：2014-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Seok SEOL ,  Seung-Jun BAE ,  Young-Soo SOHN ,  Ho-Sung SONG

IPC: H03K19/00

CPC classification number: H03K19/0005

Abstract: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.

Abstract translation: 片上终端（ODT）电路包括校准单元，偏移码生成单元，加法器和ODT单元。 校准单元生成一个上拉代码和一个下拉代码。 偏移码基于模式寄存器设置信号，上拉代码和下拉码产生上拉偏移码和下拉偏移码。 加法器分别将上拉偏移代码和下拉偏移代码加到上拉代码和下拉代码，并产生一个上拉校准代码和一个下拉校准代码。 ODT单元根据上拉校准代码和下拉校准代码改变ODT电阻。

公开(公告)号：US20140219036A1

公开(公告)日：2014-08-07

申请号：US14165990

申请日：2014-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Hyun KIM ,  Seung-Jun BAE ,  Kyung-Soo HA

IPC: G11C7/12 ,  H03K19/094 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/1048 ,  G11C7/1057 ,  H03K19/00361 ,  H03K19/09429

Abstract: Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

Abstract translation: 提供了一种均衡器和包括该均衡器的半导体存储器件。 均衡器包括延迟电路和反相电路。 延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。 反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。 均衡器被配置为使得当延迟电路输出延迟信号时，均衡器用作放大输入信号并输出​​放大的输入信号的感应偏置电路，并且当延迟电路输出反相信号时，均衡器作为锁存器 电路存储和输出输入信号。