公开(公告)号：US20230281792A1

公开(公告)日：2023-09-07

申请号：US18060260

申请日：2022-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooryong LEE ,  Jaewon YANG ,  Kyoung Cho NA ,  Jihong KIM ,  Sang Chul YEO ,  Hyeok LEE

IPC: G06T7/00 ,  G06T11/00 ,  G06T3/40 ,  G06F30/392

CPC classification number: G06T7/001 ,  G06T11/00 ,  G06T3/40 ,  G06F30/392 ,  G06T2207/30148 ,  G06T2207/20081

Abstract: Disclosed is an operating method of an electronic device which includes a processor executing a semiconductor layout simulation module based on machine learning. The operating method includes receiving, at the semiconductor layout simulation module executed by the processor, a layout image, inferring a wafer image based on the layout image and a fabrication device information image of a semiconductor fabrication device fabricating a semiconductor integrated circuit based on a final layout image, adjusting the layout image when the wafer image is not acceptable, and confirming the layout image as the final layout image when the wafer image is acceptable.

公开(公告)号：US20230148126A1

公开(公告)日：2023-05-11

申请号：US17901368

申请日：2022-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye Ran LEE ,  Kyung Soo KIM ,  Kyoung Cho NA ,  Se Ryeun YANG

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/10814 ,  H01L27/10897 ,  H01L27/10826 ,  H01L29/7851 ,  H01L29/0847 ,  H01L29/6656

Abstract: A semiconductor memory device includes a substrate including cell and peripheral regions, a cell gate electrode disposed at the cell region, a bit line structure disposed at the cell region and including a cell conductive line and a cell line capping film disposed thereon, fin-type patterns disposed at the peripheral region, a peripheral gate electrode crossing the fin-type patterns, a peripheral gate separation pattern disposed on a sidewall of the peripheral gate electrode and having an upper surface higher than an upper surface of the peripheral gate electrode, and a peripheral interlayer insulating film covering the peripheral gate electrode, the peripheral gate separation pattern and a portion of a sidewall of the peripheral gate separation pattern. An upper surface of the peripheral interlayer insulating film and an uppermost surface of the cell line capping film are positioned at the same height relative to the substrate.