METHOD AND APPARATUS WITH SEMICONDUCTOR PATTERN CORRECTION

    公开(公告)号:US20240193415A1

    公开(公告)日:2024-06-13

    申请号:US18356612

    申请日:2023-07-21

    CPC classification number: G06N3/08

    Abstract: A processor-implemented method including generating a first corrected result image of a first desired pattern image using a backward correction neural network provided an input based on the first desired pattern image, the backward correction neural network performing a backward correction of a first process, generating a first simulated result image using a forward simulation neural network based on the first corrected result image, the forward simulation neural network performing a forward simulation of a performance of the first process, and updating the first corrected result image so that an error between the first desired pattern image and the first simulated result image is reduced.

    SEMICONDUCTOR SUBSTRATE INSPECTION DEVICE

    公开(公告)号:US20250123243A1

    公开(公告)日:2025-04-17

    申请号:US18670118

    申请日:2024-05-21

    Abstract: A semiconductor substrate inspection device is provided and includes: a function generator that generates a first signal and a second signal; an ultrasonic generator that receives the first signal generated from the function generator, generates an ultrasonic wave based on the first signal, and generates a surface wave signal on an upper surface of a substrate using the ultrasonic wave; and an electron beam measurer that inspects the surface wave signal, wherein the electron beam measurer includes: a laser light source that receives the second signal generated from the function generator and generates a first pulse laser beam based on the second signal; an electron beam generator that receives the first pulse laser beam and generates an electron beam that is emitted onto the upper surface of the substrate; and a backscattered electron detector that detects backscattered electrons generated based on the electron beam being incident on the substrate.

    CONTOUR PROBABILITY PREDICTION METHOD
    5.
    发明公开

    公开(公告)号:US20240303824A1

    公开(公告)日:2024-09-12

    申请号:US18594453

    申请日:2024-03-04

    Abstract: Provided is a contour probability prediction method of probabilistically predicting a contour, the contour probability prediction method including acquiring a plurality of contour images for an image of a wafer on which a process has been performed according to a design image, calculating a contour average and a contour standard deviation from the plurality of contour images, generating a probability distribution image calculated with a predetermined probability distribution, on the basis of the contour average and the contour standard deviation, and deep-learning-training a probability prediction model by inputting the design image and the probability distribution image into the probability prediction model.

    PATTERN INSPECTION DEVICE AND PATTERN INSPECTION METHOD

    公开(公告)号:US20240413024A1

    公开(公告)日:2024-12-12

    申请号:US18532473

    申请日:2023-12-07

    Abstract: Provided is a pattern inspection method including obtaining an image of a substrate on which a pattern is formed, extracting a contour based on the image, detecting positions of a target pattern based on the contour, generating pattern inspection data by performing a curve-fitting on the detected positions of the target pattern, and analyzing the pattern based on the pattern inspection data, wherein the curve-fitting is performed by using at least one of a Sigmoid function, a hyperbolic tangent function, and a Fermi-Dirac function, and wherein the pattern inspection data includes a width in a first direction, a height in a second direction, and a pattern slope of the target pattern.

    ELECTRONIC DEVICE SUPPORTING MANUFACTURE OF SEMICONDUCTOR DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE

    公开(公告)号:US20240386635A1

    公开(公告)日:2024-11-21

    申请号:US18528275

    申请日:2023-12-04

    Abstract: Disclosed is an operating method of an electronic device which includes a processor and supports manufacture of a semiconductor device. The operating method includes receiving, at the processor, a layout image for the manufacture of the semiconductor device and a captured image generated by capturing the semiconductor device actually manufactured, aligning, at the processor, the layout image and the captured image based on a result of emphasizing edges and corners of the layout image and the captured image, and performing, at the processor, learning based on the aligned layout image and the aligned captured image such that a first modified layout image is generated from the layout image, and the semiconductor device is manufactured based on a second modified layout image generated from the layout image.

Patent Agency Ranking