公开(公告)号：US12236098B2

公开(公告)日：2025-02-25

申请号：US18322798

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

IPC: G06F3/06

Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

公开(公告)号：US20240394331A1

公开(公告)日：2024-11-28

申请号：US18608453

申请日：2024-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsu PARK ,  Kyungsoo Kim ,  Nayeon Kim ,  Jinin So ,  Kyoungwan Woo ,  Younghyun Lee ,  Jong-Geon Lee ,  Jin Jung ,  Jeonghyeon Cho

IPC: G06F17/16 ,  G06F7/501 ,  G06F13/42

Abstract: A compute express link (CXL) memory device includes a memory device storing data, and a controller configured to read the data from the memory device based on a first command received through a first protocol, select a calculation engine based on a second command received through a second protocol different from the first protocol, and control the calculation engine to perform a calculation on the read data.

公开(公告)号：US12236099B2

公开(公告)日：2025-02-25

申请号：US18455668

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F12/00 ,  G06F3/06

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240248609A1

公开(公告)日：2024-07-25

申请号：US18455668

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0683

Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

公开(公告)号：US20240201858A1

公开(公告)日：2024-06-20

申请号：US18322798

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.