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    MEMORY DEVICE FOR DETECTING FAIL CELL AND OPERATION METHOD THEREOF
    1.
    发明公开
    MEMORY DEVICE FOR DETECTING FAIL CELL AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20230148408A1

    公开(公告)日：2023-05-11

    申请号：US17982550

    申请日：2022-11-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jooyong Park ,  Wontaeck Jung ,  Nayeon Kim ,  Jiwon Seo ,  Seungyong Hyun

    IPC: G11C16/34 ,  G11C16/08

    CPC classification number: G11C16/3459 ,  G11C16/3468 ,  G11C16/08

    Abstract: An operation method of a memory device for programming memory cells to a plurality of program states includes providing a series of program pulses to selected memory cells, performing a first verification operation of verifying a target program state among the plurality of program states, performing, when the first verification operation is passed, a second verification operation of detecting fail cells among the selected memory cells to determine if these memory cells have been overprogrammed. When the number of detected fail cells is greater than or equal to a reference value, the program operation may be terminated for that location and the data may be written to another location.

    Accelerator module and computing system including the same
    3.
    发明授权
    Accelerator module and computing system including the same 有权

    公开(公告)号：US12236099B2

    公开(公告)日：2025-02-25

    申请号：US18455668

    申请日：2023-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

    IPC: G06F12/00 ,  G06F3/06

    Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

    ACCELERATOR MODULE AND COMPUTING SYSTEM INCLUDING THE SAME
    4.
    发明公开
    ACCELERATOR MODULE AND COMPUTING SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240248609A1

    公开(公告)日：2024-07-25

    申请号：US18455668

    申请日：2023-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyoungwan Woo ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Nayeon Kim ,  Jinin So

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0683

    Abstract: An accelerator module includes a plurality of memories and a controller. The controller includes a plurality of memory controllers, a plurality of processing units, and a managing circuit. The plurality of memory controllers and the plurality of memories form a plurality of memory sub-channels. The plurality of processing units perform computational operations on a plurality of data stored in or read from the plurality of memories. The managing circuit redistributes tasks performed by the plurality of processing units or changes connections between the plurality of memory controllers and the plurality of processing units in response to a first memory sub-channel and a first processing unit being in a heavy-workload state.

    MEMORY DEVICE AND SCHEDULING METHOD THEREOF
    5.
    发明公开
    MEMORY DEVICE AND SCHEDULING METHOD THEREOF 审中-公开

    公开(公告)号：US20240201858A1

    公开(公告)日：2024-06-20

    申请号：US18322798

    申请日：2023-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

    Method and apparatus with lane generation
    6.
    发明授权
    Method and apparatus with lane generation 有权

    公开(公告)号：US12272158B2

    公开(公告)日：2025-04-08

    申请号：US17862821

    申请日：2022-07-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Nayeon Kim ,  Moonsub Byeon ,  Dokwan Oh ,  Dae Hyun Ji

    IPC: G06V20/56 ,  B60W40/06

    Abstract: A method of generating lane information using a neural network includes generating a lane probability map based on an input image, generating lane feature information and depth feature information by applying the lane probability map to a second neural network, generating depth distribution information by applying the depth feature information to a third neural network, generating spatial information based on the lane feature information and the depth distribution information, generating offset information including a displacement between a position of a lane and a reference line by applying the spatial information to a fourth neural network, and generating three-dimensional (3D) lane information using the offset information.

    Memory device and scheduling method thereof
    7.
    发明授权
    Memory device and scheduling method thereof 有权

    公开(公告)号：US12236098B2

    公开(公告)日：2025-02-25

    申请号：US18322798

    申请日：2023-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Nayeon Kim ,  Kyungsoo Kim ,  Yongsuk Kwon ,  Jinin So ,  Kyoungwan Woo

    IPC: G06F3/06

    Abstract: A memory includes: a request register configured to receive a first signal including a requester identifier using a first protocol from a host and configured to output a first priority corresponding to the requester identifier; a checker module configured to receive a second signal including a command and a request type from the host and using a second protocol that is different than the first protocol, where the checker module is configured to receive the first priority from the request register, and where the checker module is configured to determine a second priority of the command based on the first priority and the request type; a command generator configured to generate an internal command for memory operation based on the command; and a memory controller configured to schedule the internal command in a command queue based on the second priority.

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