公开(公告)号：US20240405113A1

公开(公告)日：2024-12-05

申请号：US18537916

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang XU ,  Gyeom KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Yoon Tae NAM ,  Kyung Bin CHUN ,  Ryong HA ,  Yoon HEO

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. An active pattern extends in a first horizontal direction on the substrate. First to third nanosheets are sequentially spaced apart from each other in a vertical direction on the active pattern. A gate electrode extends in a second horizontal direction on the active pattern and surrounds the first to third nanosheets. A source/drain region includes a first layer disposed along side walls and a bottom surface of a source/drain trench and a second layer filling the source/drain trench. The second layer includes a first lower side wall facing a side wall of the first nanosheet and an opposite second lower side wall. A lower surface connects the first and second lower side walls and extends in the first horizontal direction. The first and second lower side walls of the second layer extend to have a constant slope in opposite directions to each other.

公开(公告)号：US20240145541A1

公开(公告)日：2024-05-02

申请号：US18313630

申请日：2023-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Hye KIM ,  Jin Bum KIM ,  Gyeom KIM ,  Young Kwang KIM ,  Kyung Bin CHUN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.

公开(公告)号：US20240153991A1

公开(公告)日：2024-05-09

申请号：US18229218

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeom KIM ,  Da Hye KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Kyung Bin CHUN

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern; a gate structure disposed on the lower pattern; and a source/drain pattern disposed on the lower pattern, and connected to each of the plurality of sheet patterns, wherein the plurality of sheet patterns include a first sheet pattern and a second sheet pattern. The second sheet pattern is disposed between the first sheet pattern and the lower pattern. A first upper width of an upper surface of the first sheet pattern is greater than a first lower width of a bottom surface of the first sheet pattern, and a second upper width of an upper surface of the second sheet pattern is smaller than a second lower width of a bottom surface of the second sheet pattern.