SEMICONDUCTOR DEVICE
    1.
    发明公开

    公开(公告)号:US20240145541A1

    公开(公告)日:2024-05-02

    申请号:US18313630

    申请日:2023-05-08

    CPC classification number: H01L29/0673 H01L29/42392 H01L29/775 H01L29/78696

    Abstract: A semiconductor device includes an active pattern including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction. The sheet patterns include an uppermost sheet pattern and a plurality of gate structures on the lower pattern and spaced apart from each other in the first direction. Each of the plurality of gate structures includes a gate electrode and a gate insulating film and a source/drain pattern between adjacent ones of the plurality of gate structures. Each of inner gate structures includes a gate electrode and a gate insulating film. A semiconductor liner film includes silicon-germanium, and contacts the gate insulating film of each of the inner gate structures. A portion of the semiconductor liner film protrudes upwardly in the first direction beyond an upper surface of the uppermost sheet pattern.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请

    公开(公告)号:US20210057317A1

    公开(公告)日:2021-02-25

    申请号:US16819318

    申请日:2020-03-16

    Abstract: A semiconductor package having a redistribution structure including a first face and a second face and a first semiconductor chip mounted on the first face. The semiconductor package may further include a first redistribution pad exposed from the second face of the redistribution structure and a second redistribution pad exposed from the second face of the redistribution structure. The semiconductor package may further include a first solder ball being in contact with the first redistribution pad and a second solder ball being in contact with the second redistribution pad. In some embodiments, a first distance of the first redistribution pad is smaller than a second distance of the second redistribution pad, the first and second distances are measured with respect to a reference plane that intersects a lower portion of the first solder ball and a lower portion of the second solder ball.

    METHOD FOR FABRICATING A SEMICONDUCTOR PACKAGE

    公开(公告)号:US20210050298A1

    公开(公告)日:2021-02-18

    申请号:US16874284

    申请日:2020-05-14

    Abstract: A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.

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