公开(公告)号：US20220123145A1

公开(公告)日：2022-04-21

申请号：US17565650

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Bum KIM ,  Gyeom KIM ,  Da Hye KIM ,  Jae Mun KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Kyung In CHOI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

公开(公告)号：US20220005946A1

公开(公告)日：2022-01-06

申请号：US17192301

申请日：2021-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun KIM ,  Dahye KIM ,  Jinbum KIM ,  Gyeom KIM ,  Dohee KIM ,  Dongwoo KIM ,  Seunghun LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417

Abstract: A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

公开(公告)号：US20240405113A1

公开(公告)日：2024-12-05

申请号：US18537916

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yang XU ,  Gyeom KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Yoon Tae NAM ,  Kyung Bin CHUN ,  Ryong HA ,  Yoon HEO

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate. An active pattern extends in a first horizontal direction on the substrate. First to third nanosheets are sequentially spaced apart from each other in a vertical direction on the active pattern. A gate electrode extends in a second horizontal direction on the active pattern and surrounds the first to third nanosheets. A source/drain region includes a first layer disposed along side walls and a bottom surface of a source/drain trench and a second layer filling the source/drain trench. The second layer includes a first lower side wall facing a side wall of the first nanosheet and an opposite second lower side wall. A lower surface connects the first and second lower side walls and extends in the first horizontal direction. The first and second lower side walls of the second layer extend to have a constant slope in opposite directions to each other.

公开(公告)号：US20220238666A1

公开(公告)日：2022-07-28

申请号：US17404078

申请日：2021-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee KIM ,  Gyeom KIM ,  Jinbum KIM ,  Jaemun KIM ,  Seunghun LEE

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088

Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

公开(公告)号：US20170352759A1

公开(公告)日：2017-12-07

申请号：US15685459

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu KIM ,  Dong Chan SUH ,  Kwan Heum LEE ,  Byeong Chan LEE ,  Cho Eun LEE ,  Su Jin JUNG ,  Gyeom KIM ,  Ji Eon YOON

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7834

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.

公开(公告)号：US20160300932A1

公开(公告)日：2016-10-13

申请号：US15187430

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Gyeom KIM ,  Hong-Sik YOON ,  Bon-Young KOO ,  Wook-Je KIM

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/13067

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract translation: 半导体器件包括衬底上的栅极图案，栅极图案下方的跨越栅极图案的多通道有源图案，并且具有不与栅极图案重叠的第一区域和与栅极图案重叠的第二区域， 多通道活性图案沿着第一区域的外周边并且包括具有浓度的杂质和多通道活性图案上的衬垫，衬垫在第一区域的侧表面上延伸并且不在第一区域的顶表面上延伸 第一个地区。 还描述了相关的制造方法。

公开(公告)号：US20240332378A1

公开(公告)日：2024-10-03

申请号：US18463488

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggwon KIM ,  Seung Geun JUNG ,  Myung Gil KANG ,  Gyeom KIM ,  Dongwon KIM

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/41733 ,  H01L21/76805 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/401 ,  H01L23/53295 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate, a lower pattern on the substrate, a channel pattern on the lower pattern, a source/drain pattern on both sides of the channel pattern, a gate structure surrounding the channel pattern, a contact electrode electrically connected to the source/drain pattern, an etch stop layer between the gate structure and the contact electrode, and a contact interface layer on the source/drain pattern. The contact interface layer may include a first region between the source/drain pattern and the contact electrode and a second region between the source/drain pattern and the etch stop layer.

公开(公告)号：US20240153991A1

公开(公告)日：2024-05-09

申请号：US18229218

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeom KIM ,  Da Hye KIM ,  Young Kwang KIM ,  Jin Bum KIM ,  Kyung Bin CHUN

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern; a gate structure disposed on the lower pattern; and a source/drain pattern disposed on the lower pattern, and connected to each of the plurality of sheet patterns, wherein the plurality of sheet patterns include a first sheet pattern and a second sheet pattern. The second sheet pattern is disposed between the first sheet pattern and the lower pattern. A first upper width of an upper surface of the first sheet pattern is greater than a first lower width of a bottom surface of the first sheet pattern, and a second upper width of an upper surface of the second sheet pattern is smaller than a second lower width of a bottom surface of the second sheet pattern.

公开(公告)号：US20240038842A1

公开(公告)日：2024-02-01

申请号：US18119037

申请日：2023-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbin CHUN ,  Gyeom KIM ,  Dahye KIM ,  Youngkwang KIM ,  Jinbum KIM

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate, a pair of nanosheets on the fin-type active region, a gate line surrounding the pair of nanosheets, the gate line including a sub-gate portion between the pair of nanosheets, a source/drain region contacting the pair of nanosheets, and a gate dielectric film between the gate line and the pair of nanosheets and between the gate line and the source/drain region, wherein the source/drain region includes a first blocking layer between the pair of nanosheets, the first blocking layer including an edge barrier enhancing portion facing the sub-gate portion, and a second blocking layer, wherein the first blocking layer includes a portion that intermittently extends in the vertical direction.

公开(公告)号：US20240006503A1

公开(公告)日：2024-01-04

申请号：US18128417

申请日：2023-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeom KIM ,  Jinbum KIM ,  Dahye KIM ,  Kyungbin CHUN

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/0673

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate including an active region; a gate structure intersecting the active region on the substrate; channel layers on the active region, spaced apart from each other and surrounded by the gate structure; and a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers. The source/drain region includes: a first semiconductor layer on side surfaces of the channel layers; a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.