公开(公告)号：US20220165721A1

公开(公告)日：2022-05-26

申请号：US17369228

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho LEE ,  Eunseok SONG ,  Keung Beum KIM ,  Kyung Suk OH ,  Eon Soo JANG

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L27/01 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

公开(公告)号：US20240088118A1

公开(公告)日：2024-03-14

申请号：US18508663

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho LEE ,  Eunseok SONG ,  Keung Beum KIM ,  Kyung Suk OH ,  Eon Soo JANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/08 ,  H01L24/16 ,  H01L27/016 ,  H01L28/90 ,  H01L2224/08147 ,  H01L2224/16147

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

公开(公告)号：US20240055395A1

公开(公告)日：2024-02-15

申请号：US18206201

申请日：2023-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manho LEE ,  Jungmin SEO ,  Kwangseob SHIN ,  Woosin CHOI ,  Junghwan CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L24/49 ,  H10B80/00 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2224/49052 ,  H01L2224/49096

Abstract: A buffer chip is wire-bonded to memory dies. A semiconductor package includes a semiconductor die stack, a first set of wire bonds connected to a first set of semiconductor dies, a second set of wire bonds connected to a second set of semiconductor dies, and the buffer chip. The second set of semiconductor dies are on the first set of semiconductor dies. The buffer chip includes a first set of die bond pads being close to the semiconductor die stack, and a second set of die bond pads being distant from the semiconductor die stack. The second set of wire bonds extends to the first set of die bond pads of the buffer chip, and the first set of wire bonds extends to the second set of die bond pads of the buffer chip.

公开(公告)号：US20230260983A1

公开(公告)日：2023-08-17

申请号：US17994880

申请日：2022-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Manho LEE ,  Keung Beum KIM ,  Kyung Suk OH

IPC: H01L25/18 ,  H01L23/34 ,  H01L23/31 ,  H01L23/538 ,  H01R12/79

CPC classification number: H01L25/18 ,  H01L23/34 ,  H01L23/3107 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/79 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a package substrate, a power module on a first surface of the package substrate, a connector on the first surface of the package substrate, the connector being horizontally spaced apart from the power module, a first semiconductor chip on a second surface of the package substrate opposite to the first surface, and a first heat radiator on the second surface of the package substrate, the first heat radiator covering the first semiconductor chip. The first semiconductor chip vertically overlaps the power module, and the first semiconductor chip is electrically connected through the package substrate to the power module.