公开(公告)号：US20240088118A1

公开(公告)日：2024-03-14

申请号：US18508663

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho LEE ,  Eunseok SONG ,  Keung Beum KIM ,  Kyung Suk OH ,  Eon Soo JANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/08 ,  H01L24/16 ,  H01L27/016 ,  H01L28/90 ,  H01L2224/08147 ,  H01L2224/16147

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

公开(公告)号：US20220165721A1

公开(公告)日：2022-05-26

申请号：US17369228

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Manho LEE ,  Eunseok SONG ,  Keung Beum KIM ,  Kyung Suk OH ,  Eon Soo JANG

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/522 ,  H01L27/01 ,  H01L23/00 ,  H01L49/02

Abstract: A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

公开(公告)号：US20190237382A1

公开(公告)日：2019-08-01

申请号：US16148471

申请日：2018-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Choon KIM ,  Woo Hyun PARK ,  Eon Soo JANG ,  Young Sang CHO

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L23/367 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.