公开(公告)号：US12199038B2

公开(公告)日：2025-01-14

申请号：US18343784

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US11728268B2

公开(公告)日：2023-08-15

申请号：US17458873

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US20230064127A1

公开(公告)日：2023-03-02

申请号：US18053487

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGJIN LEE ,  Kyungwook Kim ,  Rakhwan Kim ,  Seungyong Yoo ,  Eun-Ji Jung

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/45

Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

公开(公告)号：US11990473B2

公开(公告)日：2024-05-21

申请号：US17723532

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol Song ,  Seungha Oh ,  Rakhwan Kim ,  Minjung Park ,  Dongsoo Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions.

公开(公告)号：US11908798B2

公开(公告)日：2024-02-20

申请号：US17406887

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Kyu Han ,  Myeongsoo Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/092

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US20230343707A1

公开(公告)日：2023-10-26

申请号：US18343784

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US20230011088A1

公开(公告)日：2023-01-12

申请号：US17705343

申请日：2022-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Rakhwan Kim ,  Wandon Kim ,  Sunyoung Noh ,  Hanmin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.

公开(公告)号：US12243815B2

公开(公告)日：2025-03-04

申请号：US17680507

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Wandon Kim ,  Rakhwan Kim

IPC: H01L23/522 ,  H01L21/768 ,  H10D64/23

Abstract: A semiconductor device includes a front-end-of-line (FEOL) layer, which includes a plurality of individual devices, on a substrate, and first, second, and third metal layers sequentially stacked on the FEOL layer. The second metal layer includes an interlayer insulating layer and an interconnection line in the interlayer insulating layer. The interconnection line includes a lower via portion electrically connected to the first metal layer, an upper via portion electrically connected to the third metal layer, and a line portion between the lower via portion and the upper via portion. A line width of an upper portion of the interconnection line gradually decreases in a vertical direction away from the substrate, and a line width of a lower portion of the interconnection line gradually increases in a vertical direction away from the substrate.

公开(公告)号：US12199042B2

公开(公告)日：2025-01-14

申请号：US17590238

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Rakhwan Kim ,  Eun-Ji Jung

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20220238439A1

公开(公告)日：2022-07-28

申请号：US17458873

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.