公开(公告)号：US12176287B2

公开(公告)日：2024-12-24

申请号：US18409447

申请日：2024-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Kyu Han ,  Myeongsoo Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US11908798B2

公开(公告)日：2024-02-20

申请号：US17406887

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Kyu Han ,  Myeongsoo Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/092

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US20230343707A1

公开(公告)日：2023-10-26

申请号：US18343784

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US12048158B2

公开(公告)日：2024-07-23

申请号：US17722736

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Yujin Kim ,  Philouk Nam ,  Youngseon Son ,  Kyongwon An ,  Jumi Yun ,  Woojin Jang

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/02249 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20230066186A1

公开(公告)日：2023-03-02

申请号：US17893274

申请日：2022-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin Kang ,  Hyungjoon Kim ,  Sangsoo Lee ,  Woojin Jang ,  Dongsung Choi

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device and a method of manufacturing the same. The method may include: forming a mold stack that includes a plurality of insulating layers alternately arranged with a plurality of sacrificial layers; forming a preliminary pad portion by sequentially patterning the mold stack; forming a cell contact hole that extends through the preliminary pad portion and the sacrificial layer portions; forming a first extension portion and a plurality of second extension portions by laterally expanding the preliminary pad portion and the sacrificial layer portions; forming a first insulating liner and a sacrificial ring pattern in the first extension portion; forming an oxide liner and an insulating ring pattern in the second extension portions; forming a sacrificial plug within the cell contact hole; and replacing the sacrificial layers with gate electrodes and replacing the preliminary pad portion, the first insulating liner, and the sacrificial ring pattern with a pad portion.

公开(公告)号：US20220238439A1

公开(公告)日：2022-07-28

申请号：US17458873

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US12230568B2

公开(公告)日：2025-02-18

申请号：US17856366

申请日：2022-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungha Lee ,  Woojin Jang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

Abstract: An interconnection structure of an integrated circuit semiconductor device includes: a first conductive layer on a semiconductor substrate; an interlayer insulating layer on the first conductive layer and including a trench and a via hole; a via layer in the via hole, the via layer penetrating the interlayer insulating layer through a bottom of the trench to contact the first conductive layer, the via layer including a protrusion protruding to a height greater than a height of the trench; a barrier layer selectively on the bottom and sidewalls of the trench and on sidewalls of the via layer in the trench; a cap layer on a surface of the via layer; and a second conductive layer in the trench on the barrier layer. The cap layer is electrically connected to the first conductive layer through the via layer.

公开(公告)号：US20220199526A1

公开(公告)日：2022-06-23

申请号：US17406887

申请日：2021-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Kyu Han ,  Myeongsoo Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522

Abstract: An integrated circuit device includes a substrate and a first electrically insulating layer on the substrate. An electrically conductive contact plug is provided, which extends at least partially through the first electrically insulating layer. The contact plug includes a protrusion having a top surface that is spaced farther from the substrate relative to a top surface of a portion of the first electrically insulating layer extending adjacent the contact plug. An electrically conductive line is provided with a terminal end, which extends on a first portion of the protrusion. A second electrically insulating layer is provided, which extends on a second portion of the protrusion and on the first electrically insulating layer. The second electrically insulating layer has a sidewall, which extends opposite a sidewall of the terminal end of the electrically conductive line.

公开(公告)号：US11329063B2

公开(公告)日：2022-05-10

申请号：US16848035

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Yujin Kim ,  Philouk Nam ,  Youngseon Son ,  Kyongwon An ,  Jumi Yun ,  Woojin Jang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157 ,  H01L21/28

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20250079249A1

公开(公告)日：2025-03-06

申请号：US18791760

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom Ko ,  Kyounglim Suk ,  Jaegun Shin ,  Sanghoon Lee ,  Woojin Jang ,  Gwangjae Jeon

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/18

Abstract: A semiconductor package includes a buffer die, an intermediate core die stack on the buffer die, where the intermediate core die stack includes a plurality of intermediate core dies and a plurality of first gap filling portions that respectively overlap side surfaces of the plurality of intermediate core dies in a first direction, a top core die on the intermediate core die stack, and a second gap filling portion that overlaps side surfaces of the intermediate core die stack in the first direction and side surfaces of the top core die in the first direction.