公开(公告)号：US20240222451A1

公开(公告)日：2024-07-04

申请号：US18243818

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wandon Kim ,  Jaeseoung Park ,  Hyunwoo Kim ,  Hyunbae Lee ,  Jeonghyuk Yim ,  Hyoseok Choi

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region extending in a first direction, a gate structure extending in a second direction, a source/drain region on the active region, a first contact structure connected to the source/drain region, and a second contact structure connected to the first contact structure. The second contact structure includes a first layer including a first grain and a second layer including second grains on the first layer. Within the first layer, a maximum vertical distance between a lowermost end of the first grain and an uppermost end of the first grain is equal to a vertical distance between a lowermost end of the first layer and an uppermost end of the first layer. A size of the first grain is greater than a size of each of the second grains. A width of the first layer is greater than a width of the first contact structure.

公开(公告)号：US11778835B2

公开(公告)日：2023-10-03

申请号：US17723523

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Musarrat Hasan ,  Wandon Kim ,  Seungkeun Cha

IPC: H10B51/30 ,  H01L29/78 ,  H01L29/51 ,  H10B51/00

CPC classification number: H10B51/30 ,  H01L29/511 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/00

Abstract: A semiconductor device includes a substrate, a channel on or in the substrate, a source/drain pair respectively on opposite ends of the channel, and a gate structure on the channel between the source/drain pair, wherein the gate structure includes an interfacial layer, a ferroelectric layer, a stabilization layer, an oxygen diffusion barrier layer, and a threshold voltage control layer that are sequentially stacked on the channel.

公开(公告)号：US11664310B2

公开(公告)日：2023-05-30

申请号：US17373573

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Donggon Yoo ,  Wandon Kim

IPC: H01L23/522 ,  H01L29/06 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L29/0649 ,  H01L29/0847

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US11610975B2

公开(公告)日：2023-03-21

申请号：US17470102

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Byounghoon Lee ,  Seungkeun Cha ,  Wandon Kim

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/45 ,  H01L29/423 ,  H01L29/10

Abstract: Semiconductor devices are provided. A semiconductor device includes a first active pattern on a first region of a substrate, a pair of first source/drain patterns on the first active pattern, a first channel pattern between the pair of first source/drain patterns, and a gate electrode that extends across the first channel pattern. The gate electrode is on an uppermost surface and at least one sidewall of the first channel pattern. The gate electrode includes a first metal pattern including a p-type work function metal, a second metal pattern on the first metal pattern and including an n-type work function metal, a first barrier pattern on the second metal pattern and including an amorphous metal layer that includes tungsten (W), carbon (C), and nitrogen (N), and a second barrier pattern on the first barrier pattern. The second barrier pattern includes the p-type work function metal.

公开(公告)号：US11557656B2

公开(公告)日：2023-01-17

申请号：US17024813

申请日：2020-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jonghan Lee ,  Wandon Kim ,  Jaeyeol Song ,  Jeonghyuk Yim ,  HyungSuk Jung

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/768

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.

公开(公告)号：US11411106B2

公开(公告)日：2022-08-09

申请号：US17176248

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Weonhong Kim ,  Wandon Kim ,  Hyeonjun Baek ,  Sangjin Hyun

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including an active pattern, a gate electrode crossing the active pattern in a plan view, and a ferroelectric pattern interposed between the active pattern and the gate electrode. The gate electrode includes a work function metal pattern disposed on the ferroelectric pattern, and an electrode pattern filling a recess formed in an upper portion of the work function metal pattern. A top surface of a topmost portion of the ferroelectric pattern is lower than a bottom surface of the recess.

公开(公告)号：US20220230956A1

公开(公告)日：2022-07-21

申请号：US17535818

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Euibok Lee ,  Wandon Kim ,  Minjoo Lee ,  Hyunbae Lee

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole.

公开(公告)号：US11296078B2

公开(公告)日：2022-04-05

申请号：US16431079

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.

公开(公告)号：US11217677B2

公开(公告)日：2022-01-04

申请号：US16584464

申请日：2019-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3215 ,  H01L21/3115

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US12262558B2

公开(公告)日：2025-03-25

申请号：US17840819

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeseoung Park ,  Wandon Kim ,  Suyoung Bae ,  Dongsoo Lee ,  Dongsuk Shin ,  Doyoung Choi

IPC: H10D84/85 ,  H01L21/02 ,  H10D30/01 ,  H10D30/67 ,  H10D30/69 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.