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1.发明公开公开(公告)号：US20230152976A1
公开(公告)日：2023-05-18
申请号：US17986021
申请日：2022-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suhyun Kim , Taeeun Park , Yukyeong Kim , Yejin Shin , Donggeun Lim , Seonghoon Woo
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0653 , G06F3/0679
Abstract: A memory system may include a plurality of first memory devices; and a memory controller that may include a first chip enable (CE) pin configured to output a first CE signal that enables selectively any one of the first memory devices and a first status input pin configured to receive a first output signal indicating a memory operation status of an enabled first memory device from among the first memory devices in a first memory operation status checking period. In the first memory operation status checking period, the first output signal has one of a first level to indicate a first status of the memory operation status of the enabled first memory device, a second level to indicate a second status of the memory operation status of the enabled first memory device, or a third level to indicate a disabled status of the first memory devices.
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公开(公告)号：US11360711B2
公开(公告)日：2022-06-14
申请号：US17092860
申请日：2020-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chulseung Lee , Seonghoon Woo , Kyuwook Han , Daehyun Kim
Abstract: A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.
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Patent Agency Ranking
3.发明授权公开(公告)号：US10754800B2
公开(公告)日：2020-08-25
申请号：US16181813
申请日：2018-11-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： WooSeong Cheong , Seonghoon Woo
Abstract: A storage device includes a controller and a nonvolatile memory device. The controller includes a field programmable gate array (FPGA) and receives an FPGA image for updating the FPGA from an outside in response to a first command received from the outside. The nonvolatile memory device stores the FPGA image. The controller receives the FPGA image through a main interface or a sideband interface, and executes the FPGA image in response to a second command received from the outside.
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公开(公告)号：US10564876B2
公开(公告)日：2020-02-18
申请号：US15804226
申请日：2017-11-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonghoon Woo , Soon Suk Hwang
Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.
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公开(公告)号：US10509575B2
公开(公告)日：2019-12-17
申请号：US15404229
申请日：2017-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seonghoon Woo , Haksun Kim , Taemin Jeong , Kyuwook Han , Soon Suk Hwang
IPC: G06F3/06 , G06F12/14 , G06F9/4401
Abstract: A storage device includes a nonvolatile memory device, and a controller configured to control the nonvolatile memory device based on metadata. The controller encrypts the metadata and loads the encrypted metadata on a random access memory of an external host device.
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公开(公告)号：US11287992B2
公开(公告)日：2022-03-29
申请号：US16793584
申请日：2020-02-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seonghoon Woo , Soon Suk Hwang
Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.
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公开(公告)号：US10831405B2
公开(公告)日：2020-11-10
申请号：US15960644
申请日：2018-04-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chulseung Lee , Seonghoon Woo , Kyuwook Han , Daehyun Kim
Abstract: A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.
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