SELF-SELECTING MEMORY DEVICES
    1.
    发明公开

    公开(公告)号:US20230389337A1

    公开(公告)日:2023-11-30

    申请号:US18108117

    申请日:2023-02-10

    CPC classification number: H10B63/24 H10B63/84

    Abstract: A self-selecting memory device includes a first conductive line on a substrate, a first memory cell on the first conductive line, a second conductive line on the first memory cell, a second memory cell on the second conductive line, and a third conductive line on the second memory cell. The first memory cell includes a first electrode, a first switching memory unit and a second electrode sequentially and vertically stacked. The second memory cell includes a third electrode, a second switching memory unit and a fourth electrode sequentially and vertically stacked. The first switching memory unit includes a first SSM pattern contacting an upper surface of the first electrode and including an OTS material, and a first nitrogen-containing pattern contacting an upper surface of the first SSM pattern and a lower surface of the second electrode and including an OTS material doped with nitrogen.

    VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20250063957A1

    公开(公告)日:2025-02-20

    申请号:US18657229

    申请日:2024-05-07

    Abstract: According to an aspect of the disclosure, a vertical memory device may include: a substrate; a plurality of electrode structures extending in a vertical direction on the substrate; a word line cut disposed apart from the plurality of electrode structures in a horizontal direction and extending in the vertical direction; and a gate stack structure may include gate electrodes and interlayer insulating layers alternately stacked on the substrate along a sidewall of each of the plurality of electrode structures and the word line cut, wherein the gate electrodes may be electrically connected to the plurality of electrode structures. In a plan view, the word line cut may be wavy-shaped.

    SEMICONDUCTOR MEMORY DEVICES AND MANUFACTURING METHODS THEREOF

    公开(公告)号:US20250017021A1

    公开(公告)日:2025-01-09

    申请号:US18630647

    申请日:2024-04-09

    Abstract: An integrated circuit device including first and second vertical transistors, wherein the first and second vertical transistors are apart from each other in a first direction; a common plate between the first and second vertical transistors; a first capacitor structure between the first vertical transistor and the common plate including a first lower electrode extending in the first direction, a first dielectric layer on the first lower electrode, and a first upper electrode on the first dielectric layer; and a second capacitor structure between the second vertical transistor and the common plate including a second lower electrode extending in the first direction, a second dielectric layer on the second lower electrode, and a second upper electrode on the second dielectric layer, wherein the first upper electrode is on a lower surface of the common plate, and the second upper electrode is on an upper surface of the common plate.

    VARIABLE RESISTANCE MEMORY DEVICE

    公开(公告)号:US20210104671A1

    公开(公告)日:2021-04-08

    申请号:US16741936

    申请日:2020-01-14

    Abstract: A semiconductor device includes a plurality of first conductive lines disposed on a substrate, a plurality of second conductive lines intersecting the plurality of first conductive lines, and a plurality of cell structures interposed between the plurality of first conductive lines and the plurality of second conductive lines. At least one among the plurality of cell structures includes a first electrode, a switching element disposed on the first electrode, a second electrode disposed on the switching element, a first metal pattern disposed on the second electrode, a variable resistance pattern interposed between the first metal pattern and at least one among the plurality of second conductive lines, and a first spacer disposed on a sidewall of the variable resistance pattern, a sidewall of the first metal pattern and a sidewall of the second electrode.

    VARIABLE RESISTANCE MEMORY DEVICE
    5.
    发明申请

    公开(公告)号:US20200075854A1

    公开(公告)日:2020-03-05

    申请号:US16426216

    申请日:2019-05-30

    Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

    VERTICAL MEMORY DEVICE
    6.
    发明申请

    公开(公告)号:US20250169080A1

    公开(公告)日:2025-05-22

    申请号:US18924249

    申请日:2024-10-23

    Abstract: A vertical memory device includes a substrate; a stack structure comprising a plurality of isolation insulating layers and a plurality of word line plates which are alternately stacked on the substrate along a vertical direction; and a plurality of electrode structures disposed on the substrate. Each of the plurality of electrode structures includes a single-crystal silicon filler extending on the substrate along the vertical direction, penetrating the plurality of isolation insulating layers and the plurality of word line plates, and contacting the substrate; and a plurality of variable resistance layers spaced apart from each other along the vertical direction, and partially covering a sidewall of the single-crystal silicon filler. Each variable resistance layer is arranged between the single-crystal silicon filler and two of the word line plates.

    SEMICONDUCTOR DEVICES
    7.
    发明申请

    公开(公告)号:US20250048650A1

    公开(公告)日:2025-02-06

    申请号:US18653139

    申请日:2024-05-02

    Abstract: A semiconductor device includes first and second conductive lines respectively extending in first and second directions on a substrate. Cell structures are respectively between the first and second conductive lines and include first and second electrodes and a selector layer. First capping layers cover side surfaces of the first conductive lines and first side surfaces of the cell structures in the second direction. First interlayer insulating layers fill spaces between the first conductive lines and between the cell structures in the second direction and contact the first capping layers. Second capping layers cover second side surfaces of the cell structures in the first direction and side surfaces of the second conductive lines. Second interlayer insulating layers fill spaces between the cell structures and between the second conductive lines in the first direction and contact the second capping layers. The first and second interlayer insulating layers have different carbon contents.

    SEMICONDUCTOR DEVICE
    8.
    发明申请

    公开(公告)号:US20250151286A1

    公开(公告)日:2025-05-08

    申请号:US18680492

    申请日:2024-05-31

    Abstract: A semiconductor device includes a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction crossing the first direction; a plurality of memory cells in a plurality of areas in which the plurality of word lines and the plurality of bit lines intersect; and a semiconductor element connected to at least one of the plurality of word lines and the plurality of bit lines, the semiconductor element including a first active pattern and a second active pattern overlapping the first active pattern along a height direction perpendicular to the first and second directions.

    THREE-DIMENSIONAL (3D) VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING SAME

    公开(公告)号:US20240422970A1

    公开(公告)日:2024-12-19

    申请号:US18529007

    申请日:2023-12-05

    Inventor: Seulji SONG

    Abstract: A 3D vertical memory device includes a substrate and an electrode structure extending in a vertical direction on the substrate. The electrode structure has a shape of a first cylinder and includes a first electrode and a switching material layer. A gate stack structure includes a gate electrode and an interlayer insulating layer alternately stacked on the substrate along a sidewall of the electrode structure. The gate electrode is electrically connected to the switching material layer. The electrode structure is arranged in a two-dimensional array structure on a plane perpendicular to the vertical direction, and constitutes a plurality of lines extending in a first direction. The electrode structures of two lines adjacent to each other in a second direction are arranged in a zigzag manner. A partition wall pillar having a shape of a second cylinder is arranged between the electrode structures adjacent to each other in the first direction.

    VARIABLE RESISTANCE MEMORY DEVICE
    10.
    发明申请

    公开(公告)号:US20180158872A1

    公开(公告)日:2018-06-07

    申请号:US15700154

    申请日:2017-09-10

    CPC classification number: H01L27/2463 H01L45/06 H01L45/1253

    Abstract: A variable resistance memory device may include a word line extending in a first direction, a bit line extending in a second direction crossing the first direction, a phase-changeable pattern provided between the word line and the bit line, a bottom electrode provided between the phase-changeable pattern and the word line, and a spacer provided on a side surface of the bottom electrode and between the phase-changeable pattern and the word line. The bottom electrode may include a first portion and a second portion, and the second portion is provided between the first portion and the spacer. The first and second portions of the bottom electrodes may have different lengths from each other in the second direction.

Patent Agency Ranking