公开(公告)号：US20190326355A1

公开(公告)日：2019-10-24

申请号：US16161370

申请日：2018-10-16

申请人： Samsung Electronics Co., Ltd.

发明人： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

公开(公告)号：US20230389337A1

公开(公告)日：2023-11-30

申请号：US18108117

申请日：2023-02-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Doyoun PARK ,  Seulji SONG ,  Yoonjong SONG

IPC分类号： H10B63/00

CPC分类号： H10B63/24 ,  H10B63/84

摘要： A self-selecting memory device includes a first conductive line on a substrate, a first memory cell on the first conductive line, a second conductive line on the first memory cell, a second memory cell on the second conductive line, and a third conductive line on the second memory cell. The first memory cell includes a first electrode, a first switching memory unit and a second electrode sequentially and vertically stacked. The second memory cell includes a third electrode, a second switching memory unit and a fourth electrode sequentially and vertically stacked. The first switching memory unit includes a first SSM pattern contacting an upper surface of the first electrode and including an OTS material, and a first nitrogen-containing pattern contacting an upper surface of the first SSM pattern and a lower surface of the second electrode and including an OTS material doped with nitrogen.

公开(公告)号：US20210005663A1

公开(公告)日：2021-01-07

申请号：US17027980

申请日：2020-09-22

申请人： Samsung Electronics Co., Ltd.

发明人： Myoungsu SON ,  Seung Pil KO ,  Jung Hyuk LEE ,  Shinhee HAN ,  Gwan-Hyeob KOH ,  Yoonjong SONG

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

摘要： A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.

公开(公告)号：US20200020847A1

公开(公告)日：2020-01-16

申请号：US16286718

申请日：2019-02-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kilho LEE ,  Gwanhyeob KOH ,  Yongjae KIM ,  Yoonjong SONG

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12

摘要： A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.