公开(公告)号：US20200075605A1

公开(公告)日：2020-03-05

申请号：US16403795

申请日：2019-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Kwang-Soo KIM ,  Bonghyun CHOI ,  Siwan KIM

IPC: H01L27/115

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

公开(公告)号：US20210175173A1

公开(公告)日：2021-06-10

申请号：US17021321

申请日：2020-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun SHIN ,  Siwan KIM ,  Bonghyun CHOI

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

公开(公告)号：US20240315021A1

公开(公告)日：2024-09-19

申请号：US18183469

申请日：2023-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siwan KIM ,  Juwon IM ,  Jonghyun PARK ,  Sori LEE ,  Bongtae PARK ,  Jaejoo SHIM

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate and circuit devices; and a second semiconductor structure including a second substrate on the first semiconductor structure and having a first region and a second region, gate electrodes in the first region and stacked in a first direction, and extending in the second region by different lengths in a second direction, channel structures extending by penetrating through the gate electrodes, separation regions penetrating through the gate electrodes, extending in the second direction, spaced apart from each other in a third direction, and defining a center block region and an edge block region, and substrate insulating layers in the second substrate between the separation regions in the second region. A width of the substrate insulating layers in the third direction is greater in the edge block region than in the center block region.

公开(公告)号：US20230223346A1

公开(公告)日：2023-07-13

申请号：US18125177

申请日：2023-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun SHIN ,  Siwan KIM ,  Bonghyun CHOI

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

公开(公告)号：US20210110786A1

公开(公告)日：2021-04-15

申请号：US17023752

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyeong CHEON ,  Minkyu PARK ,  Daewon KIM ,  Siwan KIM ,  Ukhyun KIM ,  Junho LEE ,  Eunsil LIM ,  Jungwoo CHOI

IPC: G09G5/02 ,  G06T7/90 ,  G09G5/37

Abstract: An electronic device and method are disclosed herein. The electronic device includes a display, and a processor. The processor implements the method, including: acquiring a background image of a screen generated for display, a region of interest (ROI) where a user interface (UI) element is to be displayed, calculating a value indicating a shape complexity of the ROI, dividing the ROI into a plurality of clusters according to designated attributes, calculating difference values indicating a contrast between each of the plurality of clusters and the UI element, identifying a minimum difference value from among the difference values as a contrast difference value, calculating a result value indicating a degree of visibility of the UI element relative to the background image, determining an image effect to be applied to the UI element, based on the result value, and display to the altered ROI the UI element.