公开(公告)号：US09177891B2

公开(公告)日：2015-11-03

申请号：US14045648

申请日：2013-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam Kim ,  Sun-Young Park ,  Soo-Ho Shin ,  Kye-Hee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Chang-Hyun Cho ,  Hyeong-Sun Hong

IPC: H01L23/52 ,  H01L23/48 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US09099325B2

公开(公告)日：2015-08-04

申请号：US14109517

申请日：2013-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

公开(公告)号：US09536868B2

公开(公告)日：2017-01-03

申请号：US14875385

申请日：2015-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keun-Nam Kim ,  Sun-Young Park ,  Soo-Ho Shin ,  Kye-Hee Yeom ,  Hyeon-Woo Jang ,  Jin-Won Jeong ,  Chang-Hyun Cho ,  Hyeong-Sun Hong

IPC: H01L23/48 ,  H01L27/02 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

CPC classification number: H01L27/0207 ,  H01L23/48 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers.

Abstract translation: 半导体器件包括与衬底上的有源区相交并沿第一方向延伸的多个位线，形成在相邻位线之间的有源区上的接触焊盘和设置在多个位的侧壁上的多个间隔件 线条。 接触垫的上部插入在相邻间隔件之间，并且接触垫的下部具有大于相邻间隔件之间的距离的宽度。

公开(公告)号：US09299827B2

公开(公告)日：2016-03-29

申请号：US14516201

申请日：2014-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bong-Soo Kim ,  Soo-Ho Shin ,  Ho-In Ryu ,  Hyeong-Sun Hong

IPC: H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

Abstract translation: 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。