公开(公告)号：US11189333B2

公开(公告)日：2021-11-30

申请号：US16939028

申请日：2020-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Woo Ryu ,  Soojung Rho

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4076 ,  H03L7/081 ,  G11C7/06 ,  G11C5/02

Abstract: A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.

公开(公告)号：US10784184B2

公开(公告)日：2020-09-22

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Rho ,  Chisung Oh ,  Kyomin Sohn ,  Yong-Ki Kim ,  Jong-Ho Moon ,  SeungHan Woo ,  Jaeyoun Youn

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.

公开(公告)号：US11159149B2

公开(公告)日：2021-10-26

申请号：US17021367

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Rho ,  Jang-Woo Ryu ,  Hyunah An ,  Hangi Jung

IPC: H03L5/00 ,  H03K3/356 ,  G11C7/22

Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.