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    ELECTRONIC DEVICE AND CONTROL METHOD THEREOF
    1.
    发明申请
    ELECTRONIC DEVICE AND CONTROL METHOD THEREOF 审中-公开

    公开(公告)号：US20200272946A1

    公开(公告)日：2020-08-27

    申请号：US16650083

    申请日：2018-05-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-kwan SUH ,  Keshava Prasad NAGARAJA ,  Dae-hyun KIM ,  Suk-jin KIM ,  Han-su CHO ,  Hyun-jung KIM

    IPC: G06N20/10 ,  G06N3/04 ,  G06N3/08

    Abstract: Disclosed is an electronic device. The An electronic device including a storage, and a processor configured to perform convolution processing on target data and kernel data based on stride information that indicates an interval at which the kernel data is applied to the target data stored in the storage, in which the processor is further configured to divide the target data into a plurality of pieces of sub-data based on first stride information, perform the convolution processing on the plurality of pieces of sub-data and a plurality of pieces of sub-kernel data respectively corresponding to the plurality of pieces of sub-data based on second stride information that is different from the first stride information, and combine a plurality of processing results, the plurality of pieces of sub-kernel data are obtained by dividing the kernel data based on the first stride information, and the second stride information indicates that the interval at which the kernel data is applied to the target data is 1.

    METHOD AND DEVICE FOR PROCESSING VLIW INSTRUCTION, AND METHOD AND DEVICE FOR GENERATING INSTRUCTION FOR PROCESSING VLIW INSTRUCTION
    3.
    发明申请
    METHOD AND DEVICE FOR PROCESSING VLIW INSTRUCTION, AND METHOD AND DEVICE FOR GENERATING INSTRUCTION FOR PROCESSING VLIW INSTRUCTION 审中-公开
    用于处理VLIW指令的方法和装置，以及用于生成用于处理VLIW指令的指令的方法和装置

    公开(公告)号：US20170024216A1

    公开(公告)日：2017-01-26

    申请号：US15125023

    申请日：2015-03-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-kwan SUH ,  Suk-jin KIM ,  Do-hyung KIM ,  Tai-song JIN

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50

    Abstract: Provided are a method and apparatus for processing a very long instruction word (VLIW) instruction. It is possible to effectively compress code composed of VLIW instructions, by acquiring a calculation allocation instruction including information regarding whether the VLIW instructions are allocated to a plurality of slots; updating a database including the information regarding whether the VLIW instructions are allocated to the plurality of slots based on the acquired calculation allocation instruction; and allocating at least one VLIW instruction to each of the plurality of slots based on the updated database.

    Abstract translation: 提供了用于处理非常长的指令字（VLIW）指令的方法和装置。 通过获取包括关于VLIW指令是否被分配给多个时隙的信息的计算分配指令，可以有效地压缩由VLIW指令组成的代码; 基于获取的计算分配指令，更新包括关于是否将VLIW指令分配给多个时隙的信息的数据库; 以及基于更新的数据库将至少一个VLIW指令分配给所述多个时隙中的每一个。

    MULTI-THREAD PROCESSOR AND CONTROLLING METHOD THEREOF
    4.
    发明申请
    MULTI-THREAD PROCESSOR AND CONTROLLING METHOD THEREOF 审中-公开

    公开(公告)号：US20180088998A1

    公开(公告)日：2018-03-29

    申请号：US15669408

    申请日：2017-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-kwan SUH ,  Suk-jin KIM ,  Jin-sae JUNG ,  Kang-jin YOON

    IPC: G06F9/50 ,  G06F9/38 ,  G06F9/30 ,  G06N5/04

    Abstract: A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.

    FIXED LATENCY MEMORY CONTROLLER, ELECTRONIC APPARATUS AND CONTROL METHOD
    6.
    发明申请
    FIXED LATENCY MEMORY CONTROLLER, ELECTRONIC APPARATUS AND CONTROL METHOD 审中-公开

    公开(公告)号：US20170177513A1

    公开(公告)日：2017-06-22

    申请号：US15177589

    申请日：2016-06-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Suk-jin KIM ,  Dong-kwan SUH

    IPC: G06F13/16 ,  G11C7/10

    CPC classification number: G06F13/161 ,  G11C7/1072

    Abstract: A memory controller, electronic apparatus, and control method are provided. The memory controller includes a communication module configured to perform communication with a main memory and a processor configured to, based on a time duration of receiving a response corresponding to an request to access a main memory, determine the actual latency period of the request, compare the actual latency period with an estimated latency period, and perform a latency adjustment operation corresponding to a result of the comparison.

    VLIW INTERFACE DEVICE AND METHOD FOR CONTROLLING THE SAME
    7.
    发明申请
    VLIW INTERFACE DEVICE AND METHOD FOR CONTROLLING THE SAME 审中-公开

    公开(公告)号：US20170147351A1

    公开(公告)日：2017-05-25

    申请号：US15360271

    申请日：2016-11-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-chul CHO ,  Suk-jin KIM ,  Chul-soo PARK ,  Dong-kwan SUH

    IPC: G06F9/38 ,  G06F9/30 ,  G06F15/78

    Abstract: A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.

    METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA
    8.
    发明申请
    METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA 有权
    压缩和恢复配置数据的方法

    公开(公告)号：US20150280740A1

    公开(公告)日：2015-10-01

    申请号：US14671377

    申请日：2015-03-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-chul CHO ,  Do-hyung KIM ,  Suk-jin KIM ,  Si-hwa LEE

    IPC: H03M7/42

    CPC classification number: H03M7/60 ,  H03M7/30

    Abstract: A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data

    Abstract translation: 一种压缩在可重构处理器中使用的配置数据的方法，包括通过组合在两个或多个周期中使用的配置数据来生成一个组合数据，并且生成指示在组合中包括的操作中的两个或更多个周期中的每一个的有效操作的位表 数据

    PROCESSOR AND CONTROL METHODS THEREOF
    9.
    发明申请
    PROCESSOR AND CONTROL METHODS THEREOF 审中-公开

    公开(公告)号：US20190129885A1

    公开(公告)日：2019-05-02

    申请号：US16143922

    申请日：2018-09-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyoung-hoon KIM ,  Young-hwan PARK ,  Dong-kwan SUH ,  Keshava PRASAD NAGARAJA ,  Suk-jin KIM ,  Han-su CHO ,  Hyun-jung KIM

    IPC: G06F15/80 ,  G06F9/30 ,  G06F7/544 ,  G06F15/18

    Abstract: A processor for performing deep learning is provided herein. The processor includes a processing element unit including a plurality of processing elements arranged in a matrix form including a first row of processing elements and a second row of processing elements. The processing elements are fed with filter data by a first data input unit which is connected to the first row processing elements. A second data input unit feeds target data to the processing elements. A shifter composed of registers feeds instructions to the processing elements. A controller in the processor controls the processing elements, the first data input unit and second data input unit to process the filter data and target data, thus providing sum of products (convolution) functionality.

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