公开(公告)号：US08796127B2

公开(公告)日：2014-08-05

申请号：US13734306

申请日：2013-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeseok Kim ,  Hoyoung Kim ,  Bo Kyeong Kang ,  Sukhoon Jeong ,  Boun Yoon ,  Chang-Sun Hwang

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/16 ,  H01L21/70 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places.

Abstract translation: 制造半导体器件的方法包括：形成蚀刻停止层以覆盖衬底上的第一和第二伪栅极图案的侧壁和顶表面; 以及在所述衬底和所述蚀刻停止层上形成层间绝缘层。 层间绝缘层被平坦化以暴露第一和第二伪栅极图案上的蚀刻停止层，蚀刻停止层被蚀刻以暴露第一和第二伪栅极图案的顶表面和上侧壁表面，从而形成凹槽 在层间绝缘层和第一和第二伪栅极图案之间。 去除伪栅极图案，并在其位置形成栅电极。

公开(公告)号：US20130237045A1

公开(公告)日：2013-09-12

申请号：US13734306

申请日：2013-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeseok KIM ,  Hoyoung Kim ,  Bo Kyeong Kang ,  Sukhoon Jeong ,  Boun Yoon ,  Chang-Sun Hwang

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/16 ,  H01L21/70 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places.

Abstract translation: 制造半导体器件的方法包括：形成蚀刻停止层以覆盖衬底上的第一和第二伪栅极图案的侧壁和顶表面; 以及在所述衬底和所述蚀刻停止层上形成层间绝缘层。 层间绝缘层被平坦化以暴露第一和第二伪栅极图案上的蚀刻停止层，蚀刻停止层被蚀刻以暴露第一和第二伪栅极图案的顶表面和上侧壁表面，从而形成凹槽 在层间绝缘层和第一和第二伪栅极图案之间。 去除伪栅极图案，并在其位置形成栅电极。

公开(公告)号：US20250073843A1

公开(公告)日：2025-03-06

申请号：US18440747

申请日：2024-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Imbi Yeo ,  Sukhoon Jeong ,  Jonghyeon Jeong ,  Seyun Park ,  Myeongjin Lee

IPC: B24B37/32

Abstract: An example retainer ring module includes a retainer ring and at least one slurry passage. The retainer ring is arranged on a lower surface of a polishing pad to surround a substrate on an upper surface of the polishing pad to which slurry may be provided. The at least one slurry passage is formed in the retainer ring in a downward slant direction toward a central portion of the retainer ring to introduce the slurry to a space between the substrate and the polishing pad.