公开(公告)号：US20250022713A1

公开(公告)日：2025-01-16

申请号：US18633627

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongsuk Oh ,  Jinuk Byun ,  Hoyoung Kim ,  Hyunkyu Moon ,  Kiho Bae ,  Boun Yoon ,  Hojoon Lee ,  Seunghoon Choi

IPC: H01L21/304 ,  G06N3/04 ,  H01L21/66 ,  H01L21/67

Abstract: An offset data correction method includes measuring a measurement target that has undergone a chemical mechanical polishing (CMP) process, generating an offset correction model based on the measurement of the measurement target, and using the offset correction model, correcting measured data obtained from the measurement of the measurement target, wherein the offset correction model is trained by using the measured data and layout data of the measurement target as inputs.

公开(公告)号：US20240051079A1

公开(公告)日：2024-02-15

申请号：US18296021

申请日：2023-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunkyoung Kim ,  Kiho Bae ,  Hoyoung Kim ,  Boumyoung Park ,  Boun Yoon

IPC: B24B37/005 ,  G05D11/13

CPC classification number: B24B37/0056 ,  G05D11/138 ,  H01L21/31053

Abstract: A chemical mechanical polishing apparatus includes: supply pipes to which a slurry stock solution and a diluent are supplied; flow rate control units, respectively disposed on the supply pipes to control flow rates of the slurry stock solution and the diluent; a mixer connected to the flow rate control units and configured to mix the slurry stock solution and the diluent, supplied from the supply pipes, to prepare a slurry; a slurry storage unit connected to the mixer and configured to store the slurry prepared in the mixer; a slurry supply unit configured to draw out the slurry stored in the slurry storage unit and to supply the slurry to a polishing pad; and a control unit configured to control the flow rate control units to control a mixing ratio of the slurry stock solution and the diluent and a flow rate of the slurry to the polishing pad.

公开(公告)号：US09972696B2

公开(公告)日：2018-05-15

申请号：US15229930

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoung Kim ,  Sang Won Bae ,  Jae-Jik Baek ,  Wonsang Choi

IPC: H01L21/3213 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3205 ,  C09K13/00

CPC classification number: H01L29/66545 ,  C09K13/00 ,  H01L21/28017 ,  H01L21/28255 ,  H01L21/32055 ,  H01L21/32134 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure relates to an etchant, a method of making an etchant, an etching method and a method of fabricating a semiconductor device using the same. The etching method includes supplying an etchant on an etch-target layer to etch the etch-target layer in a wet etch manner. The etchant contains a basic compound and a sugar alcohol, and the basic compound contains ammonium hydroxide or tetraalkyl ammonium hydroxide. In the etchant, the sugar alcohol has 0.1 to 10 parts by weight for every 100 parts by weight of the basic compound.

公开(公告)号：US09898838B2

公开(公告)日：2018-02-20

申请号：US15073731

申请日：2016-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejun Shim ,  Kwontaek Kwon ,  Sunmin Kwon ,  Hoyoung Kim ,  Seonghun Jeong

IPC: G06T15/04 ,  G06T11/00 ,  G06T1/20

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T11/40 ,  G06T15/04 ,  G06T2210/36

Abstract: A method of determining a level of detail (LOD) for a texturing includes: acquiring texture coordinate data on pixels included in an upper block; determining a reference quad among quads included in the upper block; determining a similarity between the determined reference quad and the upper block using texture coordinates of the determined reference quad and the upper block; and determining LODs of remaining quads among the quads included in the upper block to be the same as an LOD of the determined reference quad in response to the determining of the similarity including determining that the determined reference quad and the upper block are similar.

公开(公告)号：US09006067B2

公开(公告)日：2015-04-14

申请号：US14146185

申请日：2014-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Kyeong Kang ,  Jaeseok Kim ,  Boun Yoon ,  Hoyoung Kim ,  Ilyoung Yoon

IPC: H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/823456 ,  H01L21/823481

Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.

Abstract translation: 制造半导体器件的方法包括使用蚀刻掩模图案在半导体衬底上形成第一栅极图案，在第一栅极图案之间的半导体衬底中形成沟槽，在沟槽中形成绝缘层，使得绝缘层填充 沟槽并且设置在蚀刻掩模图案上，使绝缘层平坦化，直到暴露蚀刻掩模图案的顶表面，蚀刻平坦化绝缘层的一部分以在沟槽中形成器件隔离层，形成第二栅极层覆盖层 蚀刻掩模图案并且设置在器件隔离图案上，并且平坦化第二栅极层，直到暴露出蚀刻掩模图案的顶表面，使得形成第二栅极图案。

公开(公告)号：US12069011B2

公开(公告)日：2024-08-20

申请号：US17503819

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyeon Lee ,  Hoyoung Kim ,  Jaehyung An ,  Dongil Yang ,  Cheolseung Jung

IPC: H04L51/04 ,  G06F40/20 ,  G06F40/30

CPC classification number: H04L51/04 ,  G06F40/20 ,  G06F40/30

Abstract: An electronic device and a method for controlling thereof are provided. The electronic device may include: a memory and a processor configured to: input sentences input into a plurality of conversation rooms generated through a messenger application into a first model and acquire characteristic information of conversations conducted in the plurality of respective conversation rooms, based on a first sentence being input, input the first sentence and the characteristic information into a second model and acquire first scores indicating a similarity between the first sentence and the characteristics of the conversations conducted in the plurality of respective conversation rooms, input the first sentence and the sentences input into the plurality of conversation rooms into a third model and acquire second scores indicating relevance between the first sentence and the sentences input into the plurality of conversation rooms, identify a conversation room as a conversation room corresponding to the first sentence among the plurality of conversation rooms based on the characteristic information, the first scores, and the second scores, and input the first sentence into the identified conversation room.

公开(公告)号：US20230191555A1

公开(公告)日：2023-06-22

申请号：US17940403

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chaelyoung Kim ,  Jinyoung Park ,  Jaehyug Lee ,  Hoyoung Kim

IPC: B24B37/04 ,  B24B37/10 ,  B24B57/02 ,  H01L21/3105

CPC classification number: B24B37/046 ,  B24B37/105 ,  B24B37/044 ,  B24B57/02 ,  H01L21/31053 ,  H01L21/3212

Abstract: A chemical mechanical polishing apparatus, includes: a platen having a polishing pad attached to an upper surface thereof, and rotatably installed in one direction by a driving means, a slurry supply unit supplying a slurry including an abrasive and an additive having a zeta potential of a first polarity to the polishing pad, an electrode disposed below the polishing pad, a power supply unit applying a voltage including a DC pulse of a second polarity, opposite to the first polarity, to the electrode, and a polishing head installed on the polishing pad, and rotating a semiconductor substrate in contact with the polishing pad.

公开(公告)号：US10153214B2

公开(公告)日：2018-12-11

申请号：US15386843

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Jung Park ,  Ju-Hyun Kim ,  Hoyoung Kim ,  Boun Yoon ,  TaeYong Kwon ,  Sangkyun Kim ,  Sanghyun Park

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3105 ,  H01L21/306 ,  H01L27/092

Abstract: A patterning method for fabricating a semiconductor device includes forming, for example sequentially forming, a lower buffer layer, a first channel semiconductor layer, and a capping insulating layer on a substrate, forming an opening to penetrate the capping insulating layer and the first channel semiconductor layer and expose a portion of the lower buffer layer, forming a second channel semiconductor layer to fill the opening and include a first portion protruding above the capping insulating layer, performing a first CMP process to remove at least a portion of the first portion, removing the capping insulating layer, and performing a second CMP process to remove at least a portion of a second portion of the second channel semiconductor layer protruding above the first channel semiconductor layer.

公开(公告)号：US09997412B1

公开(公告)日：2018-06-12

申请号：US15646300

申请日：2017-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Ho Bae ,  Jaeseok Kim ,  Hoyoung Kim ,  Boun Yoon ,  KyungTae Lee ,  Kwansung Kim ,  Eunji Park

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.

公开(公告)号：US11632129B2

公开(公告)日：2023-04-18

申请号：US17965141

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoyoung Kim

IPC: H03M7/00 ,  H03M7/30 ,  G06N3/02 ,  H03M7/46 ,  H03M7/40 ,  G06N3/063 ,  G06N3/082

Abstract: A method of compressing weights of a neural network includes compressing a weight set including the weights of a the neural network, determining modified weight sets by changing at least one of the weights, calculating compression efficiency values for the determined modified weight sets based on a result of compressing the weight set and results of compressing the determined modified weight sets, determining a target weight of the weights satisfying a compression efficiency condition among the weights based on the calculated compression efficiency values, and determining a final compression result by compressing the weights based on a result of replacing the determined target weight.