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    Semiconductor device and method of fabricationg the same
    1.
    发明授权
    Semiconductor device and method of fabricationg the same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US09006067B2

    公开(公告)日：2015-04-14

    申请号：US14146185

    申请日：2014-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bo Kyeong Kang ,  Jaeseok Kim ,  Boun Yoon ,  Hoyoung Kim ,  Ilyoung Yoon

    IPC: H01L21/8234

    CPC classification number: H01L21/823431 ,  H01L21/823456 ,  H01L21/823481

    Abstract: A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.

    Abstract translation: 制造半导体器件的方法包括使用蚀刻掩模图案在半导体衬底上形成第一栅极图案，在第一栅极图案之间的半导体衬底中形成沟槽，在沟槽中形成绝缘层，使得绝缘层填充 沟槽并且设置在蚀刻掩模图案上，使绝缘层平坦化，直到暴露蚀刻掩模图案的顶表面，蚀刻平坦化绝缘层的一部分以在沟槽中形成器件隔离层，形成第二栅极层覆盖层 蚀刻掩模图案并且设置在器件隔离图案上，并且平坦化第二栅极层，直到暴露出蚀刻掩模图案的顶表面，使得形成第二栅极图案。

    Methods of fabricating semiconductor devices and semiconductor devices formed thereby
    2.
    发明授权
    Methods of fabricating semiconductor devices and semiconductor devices formed thereby 有权
    制造半导体器件和由此形成的半导体器件的方法

    公开(公告)号：US08796127B2

    公开(公告)日：2014-08-05

    申请号：US13734306

    申请日：2013-01-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeseok Kim ,  Hoyoung Kim ,  Bo Kyeong Kang ,  Sukhoon Jeong ,  Boun Yoon ,  Chang-Sun Hwang

    IPC: H01L21/28

    CPC classification number: H01L21/28008 ,  H01L21/16 ,  H01L21/70 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

    Abstract: A method of fabricating a semiconductor device comprises: forming an etch stop layer to cover sidewall and top surfaces of first and second dummy gate patterns on a substrate; and forming an interlayer insulating layer on the substrate and the etch stop layer. The interlayer insulating layer is planarized to expose the etch stop layer on the first and second dummy gate patterns, and the etch stop layer is etched to expose the top surfaces and upper sidewall surfaces of the first and second dummy gate patterns, thereby forming a groove between the interlayer insulating layer and the first and second dummy gate patterns. The dummy gate patterns are removed, and gate electrodes are formed in their places.

    Abstract translation: 制造半导体器件的方法包括：形成蚀刻停止层以覆盖衬底上的第一和第二伪栅极图案的侧壁和顶表面; 以及在所述衬底和所述蚀刻停止层上形成层间绝缘层。 层间绝缘层被平坦化以暴露第一和第二伪栅极图案上的蚀刻停止层，蚀刻停止层被蚀刻以暴露第一和第二伪栅极图案的顶表面和上侧壁表面，从而形成凹槽 在层间绝缘层和第一和第二伪栅极图案之间。 去除伪栅极图案，并在其位置形成栅电极。

    Methods of manufacturing semiconductor devices
    6.
    发明授权
    Methods of manufacturing semiconductor devices 有权

    公开(公告)号：US09997412B1

    公开(公告)日：2018-06-12

    申请号：US15646300

    申请日：2017-07-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki Ho Bae ,  Jaeseok Kim ,  Hoyoung Kim ,  Boun Yoon ,  KyungTae Lee ,  Kwansung Kim ,  Eunji Park

    IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/321 ,  H01L29/66

    CPC classification number: H01L21/823475 ,  H01L21/823418 ,  H01L21/823437

    Abstract: A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.

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