公开(公告)号：US20240136425A1

公开(公告)日：2024-04-25

申请号：US18190837

申请日：2023-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edwardnamkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Sumin Yu ,  Seojin Jeong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

公开(公告)号：US20230402510A1

公开(公告)日：2023-12-14

申请号：US18100872

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namkyu CHO ,  Jungtaek Kim ,  Moon Seung Yang ,  Sumin Yu ,  Seojin Jeong ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66439

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and a source/drain pattern on a side surface of the channel pattern, the source/drain pattern including a first section between a first level and a second level that is higher than the first level, a first variation section between the second level and a third level that is higher than the second level, and a second section between the third level and a fourth level that is higher than the third level, where a rate of change in germanium concentration in the first variation section in a first direction is greater than a rate of change in germanium concentration in each of the first section and the second section in the first direction, and a germanium concentration at each of the first level and the second level is greater than 0 at % and equal to or less than 10 at %.

公开(公告)号：US20230395662A1

公开(公告)日：2023-12-07

申请号：US18299086

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/08 ,  H01L29/775 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/775 ,  H01L29/42392 ,  H01L29/0673

Abstract: Semiconductor device may include an active region extending in a first direction, channel layers spaced apart from each other in a vertical direction, a gate structure extending on the active region and the channel layers to surround the channel layers and extending in a second direction, and a source/drain region on the active region adjacent to a side of the gate structure and contacting the plurality of channel layers. The source/drain region includes first to sixth epitaxial layers that are sequentially stacked in the vertical direction and have respective first to sixth germanium (Ge) concentrations. The first Ge concentration is lower than the second Ge concentration, the third Ge concentration is lower than the second Ge concentration and the fourth Ge concentration, and the fifth Ge concentration is lower than the fourth Ge concentration and the sixth Ge concentration.

公开(公告)号：US20240234541A9

公开(公告)日：2024-07-11

申请号：US18190837

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edwardnamkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Sumin Yu ,  Seojin Jeong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

公开(公告)号：US20240030286A1

公开(公告)日：2024-01-25

申请号：US18140905

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Heo ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Edward Namkyu Cho ,  Ryong Ha

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.

公开(公告)号：US20230402459A1

公开(公告)日：2023-12-14

申请号：US18185941

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seojin Jeong ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Edward Namkyu Cho ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L29/7851 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/42392

Abstract: An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a Si1-xGex layer (x≠0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.

公开(公告)号：US20230378336A1

公开(公告)日：2023-11-23

申请号：US18117405

申请日：2023-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Cho ,  Jungtaek Kim ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Seokhoon Kim ,  Pankwi Park

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/0649 ,  H01L29/41775

Abstract: A semiconductor device includes an active region extending on a substrate in a first direction, a plurality of channel layers on the active region to be spaced apart from each other in a vertical direction, perpendicular to an upper surface of the substrate, the plurality of channel layers including silicon germanium, a gate structure intersecting the active region and the plurality of channel layers on the substrate to surround the plurality of channel layers, respectively, a source/drain region on the active region on at least one side of the gate structure, the source/drain region in contact with the plurality of channel layers, and a substrate insulating layer disposed between the source/drain region and the substrate. The source/drain region includes a first layer in contact with a side surface of the gate structure, side surfaces of the plurality of channel layers, and an upper surface of the substrate insulating layer.