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公开(公告)号：US11251313B2
公开(公告)日：2022-02-15
申请号：US16774653
申请日：2020-01-28
发明人： Seung Mo Kang , Moon Seung Yang , Jongryeol Yoo , Sihyung Lee , Sunguk Jang , Eunhye Choi
IPC分类号： H01L29/786 , H01L29/423 , H01L29/08 , H01L29/06 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/8234 , H01L21/311
摘要： A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.
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公开(公告)号：US20170373062A1
公开(公告)日：2017-12-28
申请号：US15494769
申请日：2017-04-24
发明人： Moon Seung Yang , Dong Chan SUH , Chul KIM , Woo Bin SONG , Ji Eon YOON , Seung Ryul LEE
IPC分类号： H01L27/092 , H01L29/06 , H01L29/10 , H01L29/78
摘要： The semiconductor device includes a first multi-channel active pattern protruding from a substrate, and having a first height, a second multi-channel active pattern on the substrate, being spaced apart from the substrate, and having a second height that is less than the first height, and a gate electrode on the substrate, intersecting the first multi-channel active pattern and the second multi-channel active pattern.
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公开(公告)号：US20230402510A1
公开(公告)日：2023-12-14
申请号：US18100872
申请日：2023-01-24
发明人： Namkyu CHO , Jungtaek Kim , Moon Seung Yang , Sumin Yu , Seojin Jeong , Seokhoon Kim , Pankwi Park
IPC分类号： H01L29/08 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/66
CPC分类号： H01L29/0847 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/66439
摘要： A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, and a source/drain pattern on a side surface of the channel pattern, the source/drain pattern including a first section between a first level and a second level that is higher than the first level, a first variation section between the second level and a third level that is higher than the second level, and a second section between the third level and a fourth level that is higher than the third level, where a rate of change in germanium concentration in the first variation section in a first direction is greater than a rate of change in germanium concentration in each of the first section and the second section in the first direction, and a germanium concentration at each of the first level and the second level is greater than 0 at % and equal to or less than 10 at %.
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公开(公告)号：US11569389B2
公开(公告)日：2023-01-31
申请号：US17470341
申请日：2021-09-09
发明人： Moon Seung Yang , Eun Hye Choi , Seung Mo Kang , Yong Seung Kim , Jung Taek Kim , Min-Hee Choi
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423
摘要： A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.
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公开(公告)号：US09899272B2
公开(公告)日：2018-02-20
申请号：US15234170
申请日：2016-08-11
发明人： Poren Tang , Sunjung Steve Kim , Moon Seung Yang , Seung Hun Lee , Hyun Jung Lee , Geun Hee Jeong
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/306 , H01L21/308 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/10 , H01L29/06 , H01L27/092 , H01L21/8258
CPC分类号： H01L21/823892 , H01L21/02381 , H01L21/0245 , H01L21/02458 , H01L21/02463 , H01L21/02499 , H01L21/02532 , H01L21/0254 , H01L21/02546 , H01L21/30604 , H01L21/30612 , H01L21/308 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L29/0653 , H01L29/1054 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/20 , H01L29/2003 , H01L29/78
摘要： Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.
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公开(公告)号：US11942551B2
公开(公告)日：2024-03-26
申请号：US17519967
申请日：2021-11-05
发明人： Jung Taek Kim , Seok Hoon Kim , Pan Kwi Park , Moon Seung Yang , Seo Jin Jeong , Min-Hee Choi , Ryong Ha
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423
CPC分类号： H01L29/78618 , H01L29/0665 , H01L29/42392 , H01L29/78696
摘要： A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.
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公开(公告)号：US11710772B2
公开(公告)日：2023-07-25
申请号：US17560865
申请日：2021-12-23
发明人： Eunhye Choi , Seung Mo Kang , Jungtaek Kim , Moon Seung Yang , Jongryeol Yoo
IPC分类号： H01L29/10 , H01L29/08 , H01L29/78 , H01L29/423 , H01L29/66
CPC分类号： H01L29/105 , H01L29/0852 , H01L29/1079 , H01L29/42356 , H01L29/66712 , H01L29/7802
摘要： A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.
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公开(公告)号：US11133421B2
公开(公告)日：2021-09-28
申请号：US16808857
申请日：2020-03-04
发明人： Moon Seung Yang , Eun Hye Choi , Seung Mo Kang , Yong Seung Kim , Jung Taek Kim , Min-Hee Choi
IPC分类号： H01L29/786 , H01L29/06 , H01L29/66 , H01L21/02 , H01L29/423
摘要： A semiconductor device includes a fin-type pattern on a substrate, the fin-type pattern extending in a first direction and protruding from the substrate in a third direction, a first wire pattern on the fin-type pattern, the first wire pattern being spaced apart from the fin-type pattern in the third direction, and a gate electrode extending in a second direction, which is perpendicular to the first and third directions, and surrounding the first wire pattern, the gate electrode including a first portion that overlaps with the fin-type pattern in the second direction and a second portion corresponding to a remainder of the gate electrode except for the first portion.
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公开(公告)号：US12021131B2
公开(公告)日：2024-06-25
申请号：US17460446
申请日：2021-08-30
发明人： Seo Jin Jeong , Do Hyun Go , Seok Hoon Kim , Jung Taek Kim , Pan Kwi Park , Moon Seung Yang , Min-Hee Choi , Ryong Ha
IPC分类号： H01L29/423 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/0665 , H01L29/0847 , H01L29/41775 , H01L29/78696
摘要： A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
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公开(公告)号：US11688813B2
公开(公告)日：2023-06-27
申请号：US17584545
申请日：2022-01-26
发明人： Seung Mo Kang , Moon Seung Yang , Jongryeol Yoo , Sihyung Lee , Sunguk Jang , Eunhye Choi
IPC分类号： H01L29/786 , H01L29/08 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/78 , H01L27/088 , H01L21/8234 , H01L21/311 , H01L21/02 , H01L21/324
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02636 , H01L21/02664 , H01L21/311 , H01L21/3247 , H01L21/823418 , H01L21/823437 , H01L21/823468 , H01L27/0886 , H01L29/0673 , H01L29/0847 , H01L29/42392 , H01L29/66545 , H01L29/66575 , H01L29/785 , H01L29/7848
摘要： A semiconductor device includes a channel pattern including first and second semiconductor patterns stacked on a substrate, a gate electrode covering top and lateral surfaces of the channel pattern and extending in a first direction, and including a first gate segment between the first semiconductor pattern and the second semiconductor pattern, a gate spacer covering a lateral surface of the gate electrode and including an opening exposing the channel pattern, and a first source/drain pattern on a side of the gate spacer and in contact with the channel pattern through the opening, the first source/drain pattern including a sidewall center thickness at a height of the first gate segment and at a center of the opening, and a sidewall edge thickness at the height of the first gate segment and at an edge of the opening, the sidewall edge thickness being about 0.7 to 1 times the sidewall center thickness.
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