公开(公告)号：US09881934B2

公开(公告)日：2018-01-30

申请号：US14495397

申请日：2014-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-min Hwang ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang

IPC: H01L27/115 ,  H01L21/265 ,  H01L21/285 ,  H01L21/306 ,  H01L21/768 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11578 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

公开(公告)号：US20180254247A1

公开(公告)日：2018-09-06

申请号：US15822329

申请日：2017-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-woo KIM ,  Joon-sung LIM ,  Jang-gn YUN ,  Sung-min Hwang

IPC: H01L23/532 ,  H01L27/11531 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L23/53295 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1207

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.

公开(公告)号：US20150263021A1

公开(公告)日：2015-09-17

申请号：US14726065

申请日：2015-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-min Hwang ,  Han-soo Kim

IPC: H01L27/115

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.

Abstract translation: 垂直结构的非易失性存储器件包括在衬底上垂直延伸的半导体区域，沿着半导体区域的侧壁在衬底上垂直延伸的多个存储单元串，并且包括多个存储单元和至少一个或多个第一 选择晶体管，它们设置在存储单元的侧面并彼此相邻。 多个字线连接到存储单元串的存储单元。 第一选择线连接到存储单元串的选择晶体管，绝缘区形成为相邻存储单元串的第一选择晶体管之间的气隙。

公开(公告)号：US09406688B2

公开(公告)日：2016-08-02

申请号：US14726065

申请日：2015-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-min Hwang ,  Han-soo Kim

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.

Abstract translation: 垂直结构的非易失性存储器件包括在衬底上垂直延伸的半导体区域，沿着半导体区域的侧壁在衬底上垂直延伸的多个存储单元串，并且包括多个存储单元和至少一个或多个第一 选择晶体管，它们设置在存储单元的侧面并彼此相邻。 多个字线连接到存储单元串的存储单元。 第一选择线连接到存储单元串的选择晶体管，绝缘区形成为相邻存储单元串的第一选择晶体管之间的气隙。

公开(公告)号：US20130279233A1

公开(公告)日：2013-10-24

申请号：US13921554

申请日：2013-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-min Hwang ,  Han-soo Kim ,  Won-seok CHO ,  Jae-hoon Jang ,  Sun-il Shim ,  Jae-hun Jeong ,  Ki-hyun Kim

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device is structured/fabricated to include a substrate, groups of memory cell strings each having a plurality of memory transistors distributed vertically so that the memory throughout multiple layers on the substrate, integrated word lines coupled to sets of the memory transistors, respectively, and stacks of word select lines. The memory transistors of each set are those transistors, of one group of the memory cell strings, which are disposed in the same layer above the substrate. The word select lines are respectively connected to the integrated word lines.

Abstract translation: 垂直非易失性存储器件被构造/制造成包括衬底，每组具有多个垂直分布的存储器晶体管的存储单元串组，使得衬底上多层的存储器，与存储器组合耦合的集成字线 晶体管和字选择线的堆叠。 每组的存储晶体管是一组存储单元串的晶体管，它们设置在衬底上方的相同层中。 字选择线分别连接到集成字线。