公开(公告)号：US20180129563A1

公开(公告)日：2018-05-10

申请号：US15718143

申请日：2017-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsik KIM ,  Tae-Hwan KIM

IPC: G06F11/10 ,  G06F12/1009 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F12/1009 ,  G06F2212/65 ,  G06F2212/7201 ,  G11C29/52

Abstract: A memory system includes a nonvolatile memory device, a dynamic random access memory (DRAM) configured to store an address mapping table for an access to the nonvolatile memory device, and a controller configured to store, in the DRAM, the address mapping table that is divided in units of address mapping data, each of the units having a size of an interface of the DRAM, read, from the stored address mapping table, target address mapping data corresponding to a logical address that is received from a host, the target address mapping data including a target parity and physical addresses of the nonvolatile memory device, and perform an error correction on the read target address mapping data, using the target parity.

公开(公告)号：US20170084477A1

公开(公告)日：2017-03-23

申请号：US15191557

申请日：2016-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Joo KANG ,  Tae-Hwan KIM

IPC: H01L21/683

CPC classification number: H01L21/6838 ,  H01L21/6875

Abstract: A substrate supporter, including a plate; and a plurality of vacuum fins protruding from the plate, each of the vacuum fins having a vacuum hole penetrating through the plate, and each of the vacuum fins including a substrate mounting surface contacting a substrate.

公开(公告)号：US20150178155A1

公开(公告)日：2015-06-25

申请号：US14580815

申请日：2014-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namshik KIM ,  Tae-Hwan KIM ,  Daewook KIM ,  Biwoong CHUNG ,  Junjin KONG

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1012 ,  G11C11/419

Abstract: A storage device is provided which includes an ECC circuit. At a write operation, the ECC circuit generates a CRC (cyclic redundancy check) parity corresponding to data and generates an ECC (error correction code) parity corresponding to the data using an error correction code. At a read operation about the data stored in the at least one nonvolatile memory device, the ECC circuit corrects an error of the data using the CRC parity and the ECC parity.

Abstract translation: 提供了一种包括ECC电路的存储装置。 在写入操作中，ECC电路产生与数据相对应的CRC（循环冗余校验）奇偶校验，并使用纠错码产生对应于数据的ECC（纠错码）奇偶校验。 在关于存储在至少一个非易失性存储器件中的数据的读取操作中，ECC电路使用CRC奇偶校验和ECC奇偶校验校正数据的错误。

公开(公告)号：US20150120257A1

公开(公告)日：2015-04-30

申请号：US14447149

申请日：2014-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Jin PARK ,  Jae-Ha KIM ,  Tae-Hwan KIM ,  Ji-Hwan HYUN

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/10

Abstract: A method of verifying operation of an oscillator includes performing a Monte-Carlo simulation with respect to points in an initial-conditions space, and then judging whether a frequency error exists. An oscillation error is determined to exist when the frequency error exists. Additional operations include determining a point at which a probability of having a settling time longer than a maximum value, of a settling time obtained up to a present time, is maximum when the frequency error does not exist. The Monte-Carlo simulation is then performed on the determined point to judge whether the frequency error exists.

Abstract translation: 验证振荡器的操作的方法包括对初始状态空间中的点执行蒙特卡罗模拟，然后判断是否存在频率误差。 当存在频率误差时，确定存在振荡误差。 附加操作包括确定当频率误差不存在时，达到当前时间之前获得的建立时间的建立时间长于其最大值的概率的点是最大的点。 然后在确定的点上执行蒙特卡罗模拟，以判断是否存在频率误差。