NETWORK SCHEDULING DEVICE AND METHOD

    公开(公告)号:US20250048352A1

    公开(公告)日:2025-02-06

    申请号:US18920417

    申请日:2024-10-18

    Abstract: A network scheduling device and method are disclosed. The scheduling method comprises: determining whether a set condition for a transmission time interval (TTI) is satisfied, and, if the set condition is satisfied, storing in a memory, at each TTI until the set TTI elapses, a data array comprising the network state of the current TTI, the scheduler type selected at the network state of the current TTI, the network state of the next TTI, and the actual compensation value for the network state of the current TTI, and updating the parameters of the first neural network based on at least one of the data arrays stored in the memory, and, if the set condition is not satisfied, inputting the network state of the current TTI to the first neural network and selecting a scheduler using the output of the first neural network based on the input network state of the current TTI.

    CONTROLLER, COMPUTING SYSTEM INCLUDING THE SAME, AND METHOD OF CREATING AND SEARCHING PAGE TABLE ENTRY FOR THE SAME

    公开(公告)号:US20220342828A1

    公开(公告)日:2022-10-27

    申请号:US17526391

    申请日:2021-11-15

    Abstract: A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

    NETWORK SWITCH AND METHOD WITH MATRIX AGGREGATION

    公开(公告)号:US20240160691A1

    公开(公告)日:2024-05-16

    申请号:US18316611

    申请日:2023-05-12

    CPC classification number: G06F17/16 G06F16/2237

    Abstract: A method of operating a network switch for collective communication includes: receiving, via a network from external electronic devices, a first and second matrix each formatted according to a sparse matrix storage format; and generating a third matrix formatted according to the sparse matrix storage format, wherein the third matrix is generated by combining the first and second matrix according to the sparse matrix storage format, wherein, according to the sparse matrix storage format the first matrix includes first matrix positions of respective first element values and the second matrix includes second matrix positions of respective second element values, and wherein the combining includes comparing the first matrix positions with the second matrix positions.

    METHOD AND APPARATUS WITH REPEATED MULTIPLICATION

    公开(公告)号:US20230385025A1

    公开(公告)日:2023-11-30

    申请号:US18187971

    申请日:2023-03-22

    CPC classification number: G06F7/5443

    Abstract: A processing device including a first buffer storing calculation rules, a calculator including a plurality of multipliers and an adder, the multipliers configured to perform multiplication repeatedly, a second buffer storing operands, the second buffer being configured to enqueue the operands based on the calculation rules into a queue, and a counter indicating a respective number indicating a number of times a multiplication is to be performed by each of the plurality of multipliers, each multiplier of the plurality of multipliers being configured to provide a non-final multiplication result to a first path to an input of the corresponding multiplier responsive to a corresponding number of multiplications performed by the multiplier being less than the respective number, and provide a final multiplication result to a second path to the adder responsive to the corresponding number of multiplications performed by the multiplier being equal to the respective number.

    DATA PROCESSING SYSTEM AND METHOD FOR ACCESSING HETEROGENEOUS MEMORY SYSTEM INCLUDING PROCESSING UNIT

    公开(公告)号:US20220398032A1

    公开(公告)日:2022-12-15

    申请号:US17837286

    申请日:2022-06-10

    Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

    STORAGE SYSTEM AND OPERATING METHOD THEREOF
    8.
    发明申请

    公开(公告)号:US20180357005A1

    公开(公告)日:2018-12-13

    申请号:US15869393

    申请日:2018-01-12

    Abstract: Provided is a removable storage system including: a data storage device configured to store a plurality of files including a first file and a second file; a host interface configured to receive, from a host, a pattern matching request including pattern information and file information regarding the plurality of files, and transmit, to the host, a result of pattern matching regarding the plurality of files; and a pattern matching accelerator configured to perform the pattern matching in response to the pattern matching request, wherein the pattern matching accelerator includes a scan engine configured to scan data based on a pattern, and a scheduler configured to control the scan engine to stop scanning the first file and start scanning the second file.

    STORAGE DEVICE, STORAGE SYSTEM, AND METHOD OF OPERATING THE STORAGE SYSTEM

    公开(公告)号:US20220083515A1

    公开(公告)日:2022-03-17

    申请号:US17341613

    申请日:2021-06-08

    Abstract: A storage system includes a storage device having a nonvolatile memory with a first and a second physical address and a host configured to insert a first journal logical address and a first target logical address into a journal mapping table. The storage device includes a flash mapping table storing the first journal logical address mapped to the first physical address, and the first target logical address mapped to the second physical address; a circuit configured to write the first journal data to an area of the nonvolatile memory to the first physical address corresponding to the first journal logical address according to the first mapping state, based on the journaling command; and to change the first mapping state of the flash mapping table to a second mapping state in which the first target logical address is remapped to the first physical address, based on the checkpointing command.

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