公开(公告)号：US11289334B2

公开(公告)日：2022-03-29

申请号：US16551930

申请日：2019-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-A Lee ,  Yeonsook Kim ,  Inji Lee

IPC: H01L29/167 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/324 ,  H01L21/322 ,  H01L27/146

Abstract: An epitaxial wafer and a method of fabricating an epitaxial wafer, the method including providing a semiconductor substrate doped with both boron and germanium such that a sum of boron concentration and germanium concentration is at least 8.5E+18 atoms/cm3 and the germanium concentration is 6 times or less the boron concentration; forming an epitaxial layer on the semiconductor substrate such that the semiconductor substrate and the epitaxial layer constitute the epitaxial wafer; and annealing the epitaxial wafer for 1 hour or longer at a temperature of 1,000° C. or less.

公开(公告)号：US12272695B2

公开(公告)日：2025-04-08

申请号：US17702408

申请日：2022-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Kim ,  Yeonsook Kim

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device is provided that includes a base substrate, an insulating film on the base substrate, and an upper substrate on the insulating film. The insulating film includes a crystalline insulating material. A thickness of the insulating film is about 1 nm to about 1,000 nm, and a thickness of the upper substrate is about 1 nm to about 100 nm.

公开(公告)号：US20230299142A1

公开(公告)日：2023-09-21

申请号：US18051907

申请日：2022-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yehwan Kim ,  Cheongjun Kim ,  Samjong Choi ,  Yeonsook Kim ,  Euido Kim ,  Gayeong Baek ,  Munkeun Lee ,  Hwon Im

IPC: H01L29/10 ,  G11C16/04 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L25/065 ,  H01L23/00 ,  H10B41/35

CPC classification number: H01L29/1079 ,  G11C16/0483 ,  H01L24/08 ,  H01L25/0657 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A memory device includes a substrate, a three-dimensional (3D) NAND memory cell array on the substrate, and a peripheral circuit including a transistor on the substrate. The substrate includes p-type impurities and n-type impurities, a concentration of the n-type impurities in the substrate is lower than a concentration of the p-type impurities in the substrate, and the concentration of the n-type impurities in the substrate is about 2×1014 atoms/cm3 to about 1.5×1015 atoms/cm3 while the concentration of the p-type impurities in the substrate is about 9×1014 atoms/cm3 to about 2×1015 atoms/cm3.