公开(公告)号：US20240074148A1

公开(公告)日：2024-02-29

申请号：US18230916

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor device includes a plurality of bit lines arranged on a substrate and extending in a first horizontal direction, a mold insulating layer arranged on the bit lines and including a plurality of openings extending in a second horizontal direction, respectively, a plurality of channel layers respectively arranged on the bit lines and including a first vertical extension portion, in each opening of the mold insulating layer, a plurality of passivation layers respectively arranged on each vertical extension portion, a gate insulating layer arranged to face each vertical extension portion with each passivation layer therebetween, and a plurality of word lines extending in the second horizontal direction on the gate insulating layer and including first word lines respectively arranged on a first sidewall of each opening of the mold insulating layer and second word lines respectively arranged on a second sidewall of each opening of the mold insulating layer.

公开(公告)号：US20230209825A1

公开(公告)日：2023-06-29

申请号：US18047109

申请日：2022-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minkyung Kang ,  Suhyeong Lee ,  Seohee Park ,  Gukhyon Yon ,  Yongsuk Tak

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: Provided is a method of manufacturing a semiconductor device, the method including: forming a mold structure comprising insulation layers and sacrificial layers alternately and repeatedly stacked on a substrate; forming a channel hole extending through the mold structure; forming a blocking layer in the channel hole; forming a charge storage layer on the blocking layer; forming a tunnel insulation layer including a doping element on the charge storage layer; performing heat treatment to diffuse the doping element from the tunnel insulation layer to the charge storage layer; and forming a channel layer on the tunnel insulation layer.

公开(公告)号：US20230352297A1

公开(公告)日：2023-11-02

申请号：US18183571

申请日：2023-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yurim KIM ,  Teawon Kim ,  Seunghee Lee ,  Seungwoo Jang ,  Yongsuk Tak

IPC: H01L21/02

CPC classification number: H01L21/02194 ,  H01L21/02205

Abstract: A method of manufacturing a semiconductor device including providing a first precursor on a substrate to adsorb a first element of the first precursor onto a first region of the substrate, providing a second precursor on the substrate to adsorb a second element of the second precursor onto a second region of the substrate, the second region being different from the first region, and providing a reactant including oxygen on the substrate to form an oxide semiconductor layer including the first element of the first precursor, the second element of the second precursor, and the oxygen of the reactant may be provided.

公开(公告)号：US20240079498A1

公开(公告)日：2024-03-07

申请号：US18236623

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghee Lee ,  Yurim Kim ,  Teawon Kim ,  Yongsuk Tak ,  Seungwoo Jang

IPC: H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is a field effect transistor including a gate electrode layer, an oxide semiconductor layer including gallium (Ga) and at least one metal element selected from indium (In) and zinc (Zn), and a dielectric layer between the gate electrode layer and the oxide semiconductor layer, wherein the oxide semiconductor layer includes a sub semiconductor layer in contact with the dielectric layer and a main semiconductor layer spaced apart from the dielectric layer with the sub semiconductor layer therebetween, the sub semiconductor layer has a first Ga content, and the first Ga content of the sub semiconductor layer is greater than contents of other metal elements included in the sub semiconductor layer and decreases as a distance from an interface of the sub semiconductor layer in contact with the dielectric layer increases.

公开(公告)号：US20240276711A1

公开(公告)日：2024-08-15

申请号：US18380848

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yurim Kim ,  Seunghee Lee ,  Seungwoo Jang ,  Yongsuk Tak

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/0335 ,  H10B12/315

Abstract: The semiconductor device may include a bit line on a substrate, a gate electrode on the bit line, a gate insulation pattern on a sidewall of the gate electrode, a first channel contacting an upper surface of the bit line and the sidewall of the gate insulation pattern and a contact plug contacting an upper surface of the first channel. The first channel may include a spinel IGZO.

公开(公告)号：US20240215225A1

公开(公告)日：2024-06-27

申请号：US18391835

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teawon Kim ,  Seohee Park ,  Yongsuk Tak ,  Minkyung Kang ,  Joonnyung Heo

IPC: H10B12/00 ,  H01L21/764

CPC classification number: H10B12/482 ,  H01L21/764 ,  H10B12/0335 ,  H10B12/315

Abstract: A semiconductor device includes a line structure on the lower structure and including a conductive pattern and an insulating capping pattern on the conductive pattern, a contact structure including a lower portion adjacent to a side surface of the line structure and an upper portion on the lower portion, a spacer structure between a side surface of the lower portion of the contact structure and the side surface of the line structure, an insulating separation pattern on the spacer structure, and a protective layer between the upper portion of the contact structure and the insulating separation pattern. The spacer structure includes an internal spacer, an external spacer, and an air gap between the internal spacer and the external spacer. Regions of the internal spacer and the external spacer exposed by the air gap include an oxide. The insulating separation pattern seals at least a portion of an upper portion of the air gap.

公开(公告)号：US20240081047A1

公开(公告)日：2024-03-07

申请号：US18351422

申请日：2023-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Teawon Kim ,  Seohee Park ,  Yongsuk Tak ,  Minkyung Kang ,  Joonnyung Heo

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34

Abstract: A semiconductor device includes a conductive pattern and a spacer structure disposed on a side surface of the conductive pattern. The spacer structure includes an inner spacer in contact with the side surface of the conductive pattern, an outer spacer spaced apart from the side surface of the conductive pattern, and an air gap disposed between the inner spacer and the outer spacer. The inner spacer includes an inner oxidized region exposed by the air gap. A concentration of oxygen in the inner oxidized region has a gradient in which the oxygen concentration decreases in a direction away from the air gap.