公开(公告)号：US20250079421A1

公开(公告)日：2025-03-06

申请号：US18757626

申请日：2024-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyun Lim ,  Yoonyoung Jeon

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498

Abstract: Provided is a semiconductor package including a first wiring structure, a second wiring structure disposed on the first wiring structure, an expanded layer electrically connecting the first wiring structure and the second wiring structure to each other, and including an expanded base layer and a plurality of via structures, a semiconductor chip disposed in the expanded layer and between the first wiring structure and the second wiring structure, and a buried capacitor structure including a plurality first through-holes spaced apart from each other that penetrate the expanded base layer adjacent to the semiconductor chip, and extend in a first horizontal direction along a side surface of the semiconductor chip, and a plurality of electrode layers disposed on sidewalls of the plurality of first through-holes.

公开(公告)号：US20240194577A1

公开(公告)日：2024-06-13

申请号：US18239167

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Jeon ,  Youngmin Kim ,  Joonseok Oh ,  Woongkeon Lee ,  Changbo Lee

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/08

Abstract: A semiconductor package includes a first redistribution structure having at least one first redistribution layer and at least one first insulating layer that are alternately stacked, a semiconductor chip electrically connected to the first redistribution structure, a second insulating layer disposed above the semiconductor chip and having an opening, a pad electrically connected to the first redistribution structure, disposed on the second insulating layer, and overlapping the opening, a pad surface layer disposed on a first region of an upper surface of the pad to overlap the opening, the pad surface layer formed of a first conductive material different from a second conductive material forming the pad. The pad has an anchor portion protruding from a second region of the upper surface of the pad. The anchor portion protrudes to a position higher than that of a lower surface of the pad surface layer.

公开(公告)号：US12237252B2

公开(公告)日：2025-02-25

申请号：US17672092

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Jeon ,  Joonseok Oh ,  Youngmin Kim ,  Dongheon Kang ,  Changbo Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package may include at least one first rewiring structure, the at least one first rewiring structure including a plurality of first insulating layers vertically stacked and a plurality of first rewiring patterns included in the plurality of first insulating layers, at least one semiconductor chip on the at least one first rewiring structure, and at least one molding layer covering the at least one semiconductor chip, wherein each of the plurality of first rewiring patterns includes, a first conductive pattern, the first conductive pattern including a curved upper surface, and a first seed pattern covering a side surface and a lower surface of the first conductive pattern, and each of the first seed patterns of the plurality of first rewiring patterns having a same shape.

公开(公告)号：US20240047357A1

公开(公告)日：2024-02-08

申请号：US18307109

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonyoung Jeon ,  Youngmin Kim ,  Joon Seok Oh ,  Changbo Lee

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L23/528 ,  H01L21/76843 ,  H01L21/76802 ,  H01L21/76877

Abstract: An interconnection structure includes a first dielectric layer, a second dielectric layer, first wiring patterns, and a first conductive pattern. The first wiring patterns respectively include a first penetration part that extends into a surface of the first dielectric layer, a first intervention part on the first penetration part and in the second dielectric layer, and a first connection part on the first intervention part and in the second dielectric layer. A top surface of the first intervention part is at a same level as a top surface of the first conductive pattern relative to the surface of the first dielectric layer. An angle between a sidewall of the first connection part and the top surface of the first intervention part is greater than that between a sidewall of the first penetration part and a bottom surface of the first dielectric layer.