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公开(公告)号：US11810957B2
公开(公告)日：2023-11-07
申请号：US17469361
申请日：2021-09-08
发明人： Juhun Park , Deokhan Bae , Jin-Wook Kim , Yuri Lee , Inyeal Lee , Yoonyoung Jung
IPC分类号： H01L29/417 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/41775 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924
摘要： Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.
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公开(公告)号：US20210384192A1
公开(公告)日：2021-12-09
申请号：US17179469
申请日：2021-02-19
发明人： Deokhan Bae , Sungmin Kim , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/092 , H01L29/78 , H01L29/66
摘要： Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
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公开(公告)号：US11315926B2
公开(公告)日：2022-04-26
申请号：US17179469
申请日：2021-02-19
发明人： Deokhan Bae , Sungmin Kim , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/092 , H01L29/78 , H01L29/66 , H01L29/423 , H01L29/08
摘要： Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
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公开(公告)号：US12029024B2
公开(公告)日：2024-07-02
申请号：US17538064
申请日：2021-11-30
发明人： Deokhan Bae , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/12 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/786 , H10B10/00
CPC分类号： H10B10/125 , H01L29/0665 , H01L29/41733 , H01L29/41791 , H01L29/42392 , H01L29/7851 , H01L29/78696
摘要： A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.
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公开(公告)号：US20230187358A1
公开(公告)日：2023-06-15
申请号：US18077281
申请日：2022-12-08
发明人： Yoonyoung Jung , Deokhan Bae , Juhun Park , Yuri Lee , Sooyeon Hong
IPC分类号： H01L23/535 , H01L27/092 , H01L23/528 , H01L29/78 , H01L29/417 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/66 , H01L21/8238
CPC分类号： H01L23/535 , H01L27/0924 , H01L23/5283 , H01L29/7851 , H01L29/41791 , H01L29/0673 , H01L29/42392 , H01L29/41733 , H01L29/775 , H01L29/66545 , H01L21/823821 , H01L21/823814 , H01L21/823871
摘要： An integrated circuit device includes: a substrate including a device area and a field area; active regions extending in a first direction in the device area; a first gate structure extending in a second direction intersecting the first direction in the device area and the field area; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact disposed on the first gate structure in the device area; and a second gate contact disposed on the second gate structure in the field area, wherein the first gate contact and the second gate contact are disposed at a level lower than an upper end of the first gate structure, and wherein a first minimum width of the first gate contact and a second minimum width of the second gate contact are different from each other.
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公开(公告)号：US11469298B2
公开(公告)日：2022-10-11
申请号：US17101703
申请日：2020-11-23
发明人： Juhun Park , Deokhan Bae , Sungmin Kim , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L29/06 , H03K19/0185 , H01L27/092
摘要： A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.
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公开(公告)号：US20220320115A1
公开(公告)日：2022-10-06
申请号：US17538064
申请日：2021-11-30
发明人： Deokhan Bae , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/11 , H01L29/78 , H01L29/417 , H01L29/06 , H01L29/423 , H01L29/786
摘要： A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.
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公开(公告)号：US12113109B2
公开(公告)日：2024-10-08
申请号：US17313638
申请日：2021-05-06
发明人： Sungmin Kim , Juhun Park , Deokhan Bae , Myungyoon Um , Yuri Lee , Inyeal Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L29/417 , H01L27/092
CPC分类号： H01L29/41791 , H01L27/0924
摘要： A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.
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公开(公告)号：US20240324165A1
公开(公告)日：2024-09-26
申请号：US18678213
申请日：2024-05-30
发明人： Deokhan Bae , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H10B10/00 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H10B10/125 , H01L29/0665 , H01L29/41733 , H01L29/41791 , H01L29/42392 , H01L29/7851 , H01L29/78696
摘要： A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.
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公开(公告)号：US11646316B2
公开(公告)日：2023-05-09
申请号：US17700590
申请日：2022-03-22
发明人： Deokhan Bae , Sungmin Kim , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0924 , H01L29/6656 , H01L29/7851
摘要： Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
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