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公开(公告)号：US11810957B2
公开(公告)日：2023-11-07
申请号：US17469361
申请日：2021-09-08
发明人： Juhun Park , Deokhan Bae , Jin-Wook Kim , Yuri Lee , Inyeal Lee , Yoonyoung Jung
IPC分类号： H01L29/417 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/41775 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0924
摘要： Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.
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公开(公告)号：US12029024B2
公开(公告)日：2024-07-02
申请号：US17538064
申请日：2021-11-30
发明人： Deokhan Bae , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/12 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/786 , H10B10/00
CPC分类号： H10B10/125 , H01L29/0665 , H01L29/41733 , H01L29/41791 , H01L29/42392 , H01L29/7851 , H01L29/78696
摘要： A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.
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公开(公告)号：US20230187358A1
公开(公告)日：2023-06-15
申请号：US18077281
申请日：2022-12-08
发明人： Yoonyoung Jung , Deokhan Bae , Juhun Park , Yuri Lee , Sooyeon Hong
IPC分类号： H01L23/535 , H01L27/092 , H01L23/528 , H01L29/78 , H01L29/417 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/66 , H01L21/8238
CPC分类号： H01L23/535 , H01L27/0924 , H01L23/5283 , H01L29/7851 , H01L29/41791 , H01L29/0673 , H01L29/42392 , H01L29/41733 , H01L29/775 , H01L29/66545 , H01L21/823821 , H01L21/823814 , H01L21/823871
摘要： An integrated circuit device includes: a substrate including a device area and a field area; active regions extending in a first direction in the device area; a first gate structure extending in a second direction intersecting the first direction in the device area and the field area; a second gate structure spaced apart from the first gate structure in the first direction; a first gate contact disposed on the first gate structure in the device area; and a second gate contact disposed on the second gate structure in the field area, wherein the first gate contact and the second gate contact are disposed at a level lower than an upper end of the first gate structure, and wherein a first minimum width of the first gate contact and a second minimum width of the second gate contact are different from each other.
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公开(公告)号：US11469298B2
公开(公告)日：2022-10-11
申请号：US17101703
申请日：2020-11-23
发明人： Juhun Park , Deokhan Bae , Sungmin Kim , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L29/06 , H03K19/0185 , H01L27/092
摘要： A semiconductor device includes a substrate having PMOSFET and NMOSFET regions spaced apart from each other in a direction, a device isolation layer provided on the substrate that defines first and second active patterns respectively on the PMOSFET and NMOSFET regions, a gate electrode crossing the first and second active patterns, first and second source/drain patterns respectively provided on the first and second active patterns respectively and near the gate electrode, and an active contact extending in the direction and coupled to the first and second source/drain patterns. The active contact includes first and second body portions, which are respectively provided on the first and the second source/drain patterns, and a first protruding portion and a recessed portion, which are provided between the first and second body portions and on the device isolation layer between the PMOSFET and NMOSFET regions. The recessed portion has an upwardly recessed bottom.
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公开(公告)号：US20220320115A1
公开(公告)日：2022-10-06
申请号：US17538064
申请日：2021-11-30
发明人： Deokhan Bae , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/11 , H01L29/78 , H01L29/417 , H01L29/06 , H01L29/423 , H01L29/786
摘要： A semiconductor memory device includes an active pattern on a substrate, the active pattern including a source/drain pattern in an upper portion thereof, a gate electrode on the active pattern and extended in a first direction, the gate electrode and the source/drain pattern adjacent to each other in a second direction that crosses the first direction, and a shared contact coupled to the source/drain pattern and the gate electrode to electrically connect the source/drain pattern and the gate electrode. The shared contact includes active and gate contacts, which are electrically connected to the source/drain pattern and the gate electrode, respectively. The gate contact includes a body portion coupled to the gate electrode and a protruding portion, which protrudes from the body portion in the second direction and extends into and buried in the active contact.
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公开(公告)号：US11996364B2
公开(公告)日：2024-05-28
申请号：US17521080
申请日：2021-11-08
发明人： Inyeal Lee , Dongbeen Kim , Jinwook Kim , Juhun Park , Deokhan Bae , Junghoon Seo , Myungyoon Um
IPC分类号： H01L23/535 , H01L23/00 , H01L23/522 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L23/535 , H01L23/5226 , H01L24/13 , H01L27/0924 , H01L29/0665 , H01L29/41733 , H01L29/41791 , H01L29/42392 , H01L29/78391 , H01L29/7851 , H01L29/78696 , H01L2224/13025
摘要： A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.
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公开(公告)号：US11327107B2
公开(公告)日：2022-05-10
申请号：US17023656
申请日：2020-09-17
发明人： Juhun Park , Juhyun Kim , Deokhan Bae , Myungyoon Um
摘要： A method of testing a semiconductor device may include preparing a semiconductor substrate in which the semiconductor substrate includes a test element group including first and second test circuits, measuring first and second leakage currents in the first and second test circuits, respectively, and calculating leakage components by comparing the first and second leakage currents. Each of the first and second test circuits may include an active region, which is an upper portion of the semiconductor substrate, a gate electrode, which is configured to cross the active region and to extend in a first direction, and an active contact, which is on the active region, is spaced apart from the gate electrode, and extends in the first direction. The second test circuit may further include a first gate contact that is connected to the gate electrode and overlaps the active region in a vertical direction perpendicular to the substrate.
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公开(公告)号：US11315926B2
公开(公告)日：2022-04-26
申请号：US17179469
申请日：2021-02-19
发明人： Deokhan Bae , Sungmin Kim , Juhun Park , Yuri Lee , Yoonyoung Jung , Sooyeon Hong
IPC分类号： H01L27/092 , H01L29/78 , H01L29/66 , H01L29/423 , H01L29/08
摘要： Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.
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公开(公告)号：US20210391464A1
公开(公告)日：2021-12-16
申请号：US17179982
申请日：2021-02-19
发明人： Deokhan Bae , Juhun Park , Myungyoon Um
IPC分类号： H01L29/78 , H01L27/088 , H01L29/417
摘要： An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.
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公开(公告)号：US10453838B2
公开(公告)日：2019-10-22
申请号：US15689418
申请日：2017-08-29
发明人： Hwichan Jun , Deokhan Bae , HeonJong Shin , Jaeran Jang , Moon Gi Cho , YoungWoo Cho
IPC分类号： H01L27/06 , H01L23/522 , H01L29/06 , H01L49/02 , H01L29/78 , H01L21/3213 , H01L23/532
摘要： A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy gate pattern on the second region of the substrate, a resistor pattern on the second region of the substrate and over the dummy gate pattern, and a connection structure coupled to each of the connection regions. The resistor pattern includes a body region and connection regions at both sides of the body region. The dummy gate pattern overlaps the body region and does not be overlap the connection regions, when viewed in a plan view.
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