公开(公告)号：US20240324218A1

公开(公告)日：2024-09-26

申请号：US18601245

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jehong OH ,  Younghwan JO ,  Seulye KIM ,  Moohyun KIM ,  Sunggil KIM

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40

Abstract: A non-volatile memory device includes a substrate including a memory cell region and a connection region, a mold structure including a plurality of gate electrodes sequentially stacked on the memory cell region and stacked stepwise on the connection region, and a plurality of mold insulating layers alternately stacked with the plurality of gate electrodes, a channel hole vertically passing through the mold structure on the memory cell region, and a channel structure disposed in the channel hole, wherein the channel structure includes a gate insulating layer, a channel layer, and a buried insulating layer sequentially disposed in the channel hole, and the channel layer includes a grain having a size of about 20 nm to about 17 μm.

公开(公告)号：US20240206174A1

公开(公告)日：2024-06-20

申请号：US18498696

申请日：2023-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seulye KIM ,  Sunhwa LIM ,  Moohyun KIM ,  Sunggil KIM ,  Yunji PARK ,  Younghwan JO

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06524

Abstract: A semiconductor device may include a gate stack including insulating and conductive patterns, which are alternately stacked on top of each other, a memory channel structure penetrating the gate stack, a selection line structure on the gate stack, and a selection channel structure penetrating the selection line structure. The selection channel structure may include a selection channel layer, which is electrically connected to the memory channel layer, and a selection insulating structure, which encloses the selection channel layer. The selection channel layer may include a connecting portion on the memory channel structure and a pillar portion on the connecting portion, and an average size of grains in the connecting portion may be less than an average size of grains in the pillar portion.