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公开(公告)号：US20220139956A1
公开(公告)日：2022-05-05
申请号：US17578965
申请日：2022-01-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hoon CHOI , Sunggil KIM , Seulye KIM , HongSuk KIM , Phil Ouk NAM , Jaeyoung AHN
IPC: H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/792 , H01L29/423 , H01L29/04 , H01L27/11565 , H01L21/02 , H01L21/306 , H01L21/3065 , H01L27/11524 , H01L27/11556
Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.
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公开(公告)号：US20200266213A1
公开(公告)日：2020-08-20
申请号：US16870082
申请日：2020-05-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji Hoon CHOI , Sung Gil KIM , Seulye KIM , Jung Ho KIM , Hong Suk KIM , Phil Ouk NAM , Jae Young AHN , Han Jin LIM
IPC: H01L27/11582 , H01L23/528 , H01L27/11565
Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
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公开(公告)号：US20190181226A1
公开(公告)日：2019-06-13
申请号：US16186915
申请日：2018-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hoon CHOI , Dongkyum KIM , Sunggil KIM , Seulye KIM , Sangsoo LEE , Hyeeun HONG
IPC: H01L29/10 , H01L27/11556 , H01L27/11582 , H01L29/423 , H01L27/11526 , H01L27/11573
Abstract: A three-dimensional semiconductor memory device includes an electrode structure including electrodes vertically stacked on a semiconductor layer, a vertical semiconductor pattern penetrating the electrode structure and connected to the semiconductor layer, and a vertical insulating pattern between the electrode structure and the vertical semiconductor pattern. The vertical insulating pattern includes a sidewall portion on a sidewall of the electrode structure, and a protrusion extending from the sidewall portion along a portion of a top surface of the semiconductor layer. The vertical semiconductor pattern includes a vertical channel portion having a first thickness and extending along the sidewall portion of the vertical insulating pattern, and a contact portion extending from the vertical channel portion and conformally along the protrusion of the vertical insulating pattern and the top surface of the semiconductor layer. The contact portion has a second thickness greater than the first thickness.
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公开(公告)号：US20190027495A1
公开(公告)日：2019-01-24
申请号：US16142637
申请日：2018-09-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji Hoon CHOI , Sung Gil KIM , Seulye KIM , Jung Ho KIM , Hong Suk KIM , Phil Ouk NAM , Jae Young AHN , Han Jin LIM
IPC: H01L27/11582 , H01L23/528 , H01L27/11565
Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
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公开(公告)号：US20180315770A1
公开(公告)日：2018-11-01
申请号：US15864410
申请日：2018-01-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hoon CHOI , Sunggil KIM , Seulye KIM , HongSuk KIM , Phil Ouk NAM , Jaeyoung AHN
IPC: H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/04 , H01L29/792 , H01L29/423
Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.
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Patent Agency Ranking
公开(公告)号：US20220384482A1
公开(公告)日：2022-12-01
申请号：US17881707
申请日：2022-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hwan KIM , Sunggil KIM , Dongkyum KIM , Seulye KIM , Ji-Hoon CHOI
IPC: H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L29/792 , H01L29/04 , H01L29/423 , H01L27/11573
Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.
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公开(公告)号：US20210043647A1
公开(公告)日：2021-02-11
申请号：US16838586
申请日：2020-04-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hwan KIM , Sunggil KIM , Dongkyum KIM , Seulye KIM , Ji-Hoon CHOI
IPC: H01L27/11582 , H01L29/04 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/423 , H01L29/792
Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.
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公开(公告)号：US20240324218A1
公开(公告)日：2024-09-26
申请号：US18601245
申请日：2024-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jehong OH , Younghwan JO , Seulye KIM , Moohyun KIM , Sunggil KIM
Abstract: A non-volatile memory device includes a substrate including a memory cell region and a connection region, a mold structure including a plurality of gate electrodes sequentially stacked on the memory cell region and stacked stepwise on the connection region, and a plurality of mold insulating layers alternately stacked with the plurality of gate electrodes, a channel hole vertically passing through the mold structure on the memory cell region, and a channel structure disposed in the channel hole, wherein the channel structure includes a gate insulating layer, a channel layer, and a buried insulating layer sequentially disposed in the channel hole, and the channel layer includes a grain having a size of about 20 nm to about 17 μm.
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公开(公告)号：US20240206174A1
公开(公告)日：2024-06-20
申请号：US18498696
申请日：2023-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seulye KIM , Sunhwa LIM , Moohyun KIM , Sunggil KIM , Yunji PARK , Younghwan JO
CPC classification number: H10B43/27 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00 , H01L2225/06524
Abstract: A semiconductor device may include a gate stack including insulating and conductive patterns, which are alternately stacked on top of each other, a memory channel structure penetrating the gate stack, a selection line structure on the gate stack, and a selection channel structure penetrating the selection line structure. The selection channel structure may include a selection channel layer, which is electrically connected to the memory channel layer, and a selection insulating structure, which encloses the selection channel layer. The selection channel layer may include a connecting portion on the memory channel structure and a pillar portion on the connecting portion, and an average size of grains in the connecting portion may be less than an average size of grains in the pillar portion.
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公开(公告)号：US20220068968A1
公开(公告)日：2022-03-03
申请号：US17523014
申请日：2021-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji Hoon CHOI , Sung Gil KIM , Seulye KIM , Jung Ho KIM , Hong Suk KIM , Phil Ouk NAM , Jae Young AHN , Han Jin LIM
IPC: H01L27/11582 , H01L23/528 , H01L27/11565
Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
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