公开(公告)号：US11606101B2

公开(公告)日：2023-03-14

申请号：US17406193

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungjun Moon ,  Dongryeol Oh ,  Younghyo Park ,  Youngjae Cho ,  Michael Choi

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/12

Abstract: An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.

公开(公告)号：US11698410B2

公开(公告)日：2023-07-11

申请号：US17471763

申请日：2021-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Hyochul Shin ,  Jinwoo Park ,  Sungno Lee ,  Younghyo Park ,  Yongki Lee ,  Heejune Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/28 ,  H03K5/24 ,  H03M1/12

CPC classification number: G01R31/2884 ,  H03K5/24 ,  H03M1/124

Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

公开(公告)号：US20220187366A1

公开(公告)日：2022-06-16

申请号：US17465337

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejune Lee ,  Jinwoo Park ,  Younghyo Park ,  Eunhye Oh ,  Sungno Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/317 ,  H03M1/10

Abstract: A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.

公开(公告)号：US11867757B2

公开(公告)日：2024-01-09

申请号：US17465337

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejune Lee ,  Jinwoo Park ,  Younghyo Park ,  Eunhye Oh ,  Sungno Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/317 ,  H03M1/10

CPC classification number: G01R31/31725 ,  G01R31/31724 ,  H03M1/1071

Abstract: A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.

公开(公告)号：US20220206062A1

公开(公告)日：2022-06-30

申请号：US17471763

申请日：2021-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Hyochul Shin ,  Jinwoo Park ,  Sungno Lee ,  Younghyo Park ,  Yongki Lee ,  Heejune Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/28 ,  H03M1/12 ,  H03K5/24

Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.