公开(公告)号：US11757462B2

公开(公告)日：2023-09-12

申请号：US17675342

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyochul Shin ,  Seungyeob Baek ,  Sungno Lee ,  Heechang Hwang ,  Michael Choi

IPC: H03M1/10 ,  H03L7/081 ,  H04B1/16 ,  H04L25/03 ,  H04L1/00

CPC classification number: H03M1/1014 ,  H03L7/0812 ,  H04B1/16 ,  H04L1/0071 ,  H04L25/03012

Abstract: An analog-to-digital conversion circuit includes; a first analog-to-digital converter (ADC), a second ADC and a third ADC collectively configured to perform conversion operations according to a time-interleaving technique, and a timing calibration circuit configured to calculate correlation values and determine differences between the correlation values using first samples generated by the first ADC, second samples generated by the second ADC, and third samples generated by the third ADC during sampling periods, wherein the timing calibration circuit is further configured to control a phase of a clock signal applied to the second ADC in response to a change in absolute value related to the differences generated during the sampling periods.

公开(公告)号：US20220206062A1

公开(公告)日：2022-06-30

申请号：US17471763

申请日：2021-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Hyochul Shin ,  Jinwoo Park ,  Sungno Lee ,  Younghyo Park ,  Yongki Lee ,  Heejune Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/28 ,  H03M1/12 ,  H03K5/24

Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

公开(公告)号：US11996857B2

公开(公告)日：2024-05-28

申请号：US17827135

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungno Lee ,  Heechang Hwang ,  Yongki Lee ,  Kyoungjun Moon ,  Hyochul Shin ,  Michael Choi

IPC: H03M1/10

CPC classification number: H03M1/1014

Abstract: An analog-to-digital conversion circuit includes analog-to-digital converters (ADCs) including a target analog-to-digital converter (ADC) providing second data samples, a first adjacent ADC providing first data samples, and a second adjacent ADC providing third data samples. The ADCs perform an analog-to-digital conversion using a time-interleaving approach in response to clock signals having different phases and including a reference clock signal. A timing calibration circuit includes a relative time skew generator generating a relative time skew and an absolute time skew generator generate an absolute time skew. A clock generator adjusts at least one phase of the clock signals based on the absolute time skew.

公开(公告)号：US11698410B2

公开(公告)日：2023-07-11

申请号：US17471763

申请日：2021-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Hyochul Shin ,  Jinwoo Park ,  Sungno Lee ,  Younghyo Park ,  Yongki Lee ,  Heejune Lee ,  Youngjae Cho ,  Michael Choi

IPC: G01R31/28 ,  H03K5/24 ,  H03M1/12

CPC classification number: G01R31/2884 ,  H03K5/24 ,  H03M1/124

Abstract: A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.

公开(公告)号：US11538479B2

公开(公告)日：2022-12-27

申请号：US17130401

申请日：2020-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-No Lee ,  Hyochul Shin ,  Hyungdong Roh ,  Yong Ki Lee

IPC: G10L15/22 ,  H04R3/00 ,  G10L15/10 ,  G10L15/28

Abstract: Disclosed is an electronic device which includes an audio processing block for voice recognition in a low-power mode. The electronic device includes a digital microphone that receives a voice signal from a user and converts the received voice signal into a PDM signal, and a DMIC interface circuit. The DMIC interface circuit includes a PDM-PCM converting block that converts the PDM signal into a PCM signal, a maxscale gain tuning block that tunes a maxscale gain of the PCM signal received from the PDM-PCM converting block based on a distance information indicating a physical distance between the user and the electronic device acquired in advance of the converting of the PDM signal, and an anti-aliasing block that performs filtering for acquiring voice data of a target frequency band associated with a PCM signal output from the maxscale gain tuning block.