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公开(公告)号：US20240021261A1
公开(公告)日：2024-01-18
申请号：US18475968
申请日：2023-09-27
发明人： Eunhye Oh , Jaehyeok Kim , Yong Ki Lee , Gapkyoung Kim , Taewook Park
CPC分类号： G11C29/42 , G11C29/4401 , G11C29/10 , G11C29/36
摘要： A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.
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公开(公告)号：US20240006008A1
公开(公告)日：2024-01-04
申请号：US18314508
申请日：2023-05-09
发明人： Taewook Park , Eunhye Oh , Jisu Kang , Yongki Lee
IPC分类号： G11C29/36
CPC分类号： G11C29/36 , G11C2029/1204
摘要： An operation method of a memory device includes programming a test pattern in a normal area, obtaining locations of error bits with respect to the test pattern and an error count for each error bit location, and repairing faulty cells included in the normal area with redundancy cells in a redundancy area based on the locations of the error bits and the error counts.
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公开(公告)号：US11804276B2
公开(公告)日：2023-10-31
申请号：US17467861
申请日：2021-09-07
发明人： Eunhye Oh , Jaehyeok Kim , Yong Ki Lee , Gapkyoung Kim , Taewook Park
CPC分类号： G11C29/42 , G11C29/10 , G11C29/36 , G11C29/4401
摘要： A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.
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公开(公告)号：US11698410B2
公开(公告)日：2023-07-11
申请号：US17471763
申请日：2021-09-10
发明人： Eunhye Oh , Hyochul Shin , Jinwoo Park , Sungno Lee , Younghyo Park , Yongki Lee , Heejune Lee , Youngjae Cho , Michael Choi
CPC分类号： G01R31/2884 , H03K5/24 , H03M1/124
摘要： A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.
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公开(公告)号：US20220187366A1
公开(公告)日：2022-06-16
申请号：US17465337
申请日：2021-09-02
发明人： Heejune Lee , Jinwoo Park , Younghyo Park , Eunhye Oh , Sungno Lee , Youngjae Cho , Michael Choi
IPC分类号： G01R31/317 , H03M1/10
摘要： A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.
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公开(公告)号：US11867757B2
公开(公告)日：2024-01-09
申请号：US17465337
申请日：2021-09-02
发明人： Heejune Lee , Jinwoo Park , Younghyo Park , Eunhye Oh , Sungno Lee , Youngjae Cho , Michael Choi
IPC分类号： G01R31/317 , H03M1/10
CPC分类号： G01R31/31725 , G01R31/31724 , H03M1/1071
摘要： A semiconductor integrated circuit includes a digital-to-analog converter and a built-in self-test circuit. The digital-to-analog converter performs a normal conversion operation to generate an analog output signal by converting a digital input signal corresponding to an external digital signal that is provided from an external device outside the semiconductor integrated circuit and provide the analog output signal to the external device. The built-in self-test circuit, while the digital-to-analog converter performs the normal conversion operation, performs a real-time monitoring operation to generate a comparison alarm signal based on the digital input signal and the analog output signal such that the comparison alarm signal indicates whether the digital-to-analog converter operates normally. Performance and reliability of the digital-to-analog converter and the semiconductor integrated circuit including the digital-to-analog converter may be enhanced by monitoring in real-time abnormality of the digital-to-analog converter using the on-time monitor.
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公开(公告)号：US11698852B2
公开(公告)日：2023-07-11
申请号：US16913707
申请日：2020-06-26
发明人： Jaeshin Lee , Eunhye Oh , Jaechul Park
CPC分类号： G06F12/0238 , G06F9/30101 , G06F9/30189 , G06F9/544 , G06F11/1451 , G06F11/1469 , G06F12/0891 , G06F13/1673 , G11C7/1039 , G06F2212/1021
摘要： A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.
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公开(公告)号：US20220206062A1
公开(公告)日：2022-06-30
申请号：US17471763
申请日：2021-09-10
发明人： Eunhye Oh , Hyochul Shin , Jinwoo Park , Sungno Lee , Younghyo Park , Yongki Lee , Heejune Lee , Youngjae Cho , Michael Choi
摘要： A test method is provided to test a semiconductor integrated circuit including an analog-to-digital converter and/or a digital-to-analog converter. An analog test signal having a test pattern is generated using an analog test signal generator or a digital test signal having the test pattern using a digital test signal generator. An analog output signal corresponding to the test pattern is generated by applying, as a digital input signal, the digital test signal having the test pattern to a digital-to-analog converter responsive to generation of the digital test signal. A digital output signal corresponding to the test pattern is generated by applying, as an analog input signal, the analog test signal having the test pattern or the analog output signal corresponding to the test pattern to an analog-to-digital converter. A normality of the semiconductor integrated circuit is determined based on the digital output signal corresponding to the test pattern.
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