公开(公告)号：US11037477B2

公开(公告)日：2021-06-15

申请号：US16572043

申请日：2019-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmook Choi ,  Boyoung Kim ,  Hwichul Kim ,  Euihyung Yoo ,  Kwansoo Lee ,  Sanghyeok Lee

IPC: G06F3/038 ,  G09G3/20

Abstract: Provided are a display apparatus, and a method and system for controlling the same, the display apparatus including: a display; an interface; a storage; and a processor configured to transmit information on a refresh rate of the display, stored in the storage, to a source apparatus connected to the interface; based on an image signal received from the source apparatus being displayed as an image on the display at a preset first refresh rate for more than a predetermined period, switch the refresh rate, stored in the storage, to a second refresh rate that is lower than the first refresh rate; transmit information about the second refresh rate to the source apparatus; and display the image on the display at the second refresh rate of the image signal received from the source apparatus.

公开(公告)号：US12082423B2

公开(公告)日：2024-09-03

申请号：US17679863

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook Choi ,  Jooheon Kang ,  Sanghoon Kim ,  Jihong Kim

IPC: H10B63/00

CPC classification number: H10B63/34

Abstract: A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.

公开(公告)号：US12165734B2

公开(公告)日：2024-12-10

申请号：US17895642

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minho Kim ,  Hyunmook Choi

IPC: G11C7/10 ,  G06F7/544 ,  G11C29/52

Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region disposed below the memory cell region. The peripheral circuits include a page buffer, a row decoder, and other peripheral circuits, wherein the page buffer is included in a page buffer block disposed on a lower surface of the first semiconductor substrate to be distinguished from other circuits included in the peripheral circuit region in a first direction perpendicular to an upper surface of the first semiconductor substrate, is connected to the memory cell region through a connection portion penetrating through the first semiconductor substrate, and includes a plurality of vertical transistors each defined by a source region, a channel region, and a drain region stacked in sequence in the first direction.

公开(公告)号：US20250169052A1

公开(公告)日：2025-05-22

申请号：US18670998

申请日：2024-05-22

Applicant: Samsung electronics Co., Ltd.

Inventor： Hyunmook Choi ,  Kangoh Yun

IPC: H10B12/00 ,  H10B41/41 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first substrate structure including a substrate, first circuit devices on the substrate, second circuit devices that extend into the substrate, a gate isolation layer penetrating the substrate and between the second circuit devices, and a second substrate structure electrically connected to the first substrate structure on the first substrate structure, and including gate electrodes electrically connected to the first and second circuit devices. Adjacent second circuit devices among the second circuit devices are disposed symmetrically with respect to the gate isolation layer.

公开(公告)号：US20240389325A1

公开(公告)日：2024-11-21

申请号：US18660799

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook Choi

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

Abstract: An integrated circuit device includes a semiconductor substrate, a gate stack including a plurality of gate layers and a plurality of insulating layers that are alternately stacked on the semiconductor substrate, a plurality of channel structures extending through the gate stack in a first direction, a word line cut extending through the gate stack in the first direction, a string selection line stack on the gate stack, and a plurality of gate structures extending through the string selection line stack in the first direction, the plurality of gate structures completely overlapping the plurality of channel structures corresponding thereto in the first direction, wherein an air gap is between two gate structures, which are adjacent to each other in an oblique direction relative to the first direction, from among the plurality of gate structures.

公开(公告)号：US20250089280A1

公开(公告)日：2025-03-13

申请号：US18809515

申请日：2024-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingyu Baek ,  Kumhyo Kang ,  Hyunmook Choi ,  Soonhyung Hong

IPC: H01G4/30

Abstract: An example semiconductor device includes a capacitor structure on a substrate. The capacitor structure includes a first electrode structure, a second electrode structure, and a capacitor dielectric layer. The first electrode structure includes first horizontal electrode portions apart from each other in a first direction perpendicular to the substrate and a first conductive pillar connected to each of the first horizontal electrode portions and extending in the first direction. The second electrode structure includes a second conductive pillar extending through the first horizontal electrode portions in the first direction and second horizontal electrode portions apart from each other in the first direction on a side wall of the second conductive pillar and alternately arranged with the first horizontal electrode portions. The capacitor dielectric layer is between the side wall of the second conductive pillar and the first horizontal electrode portions.

公开(公告)号：US20240212756A1

公开(公告)日：2024-06-27

申请号：US18390258

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook Choi ,  Jihong Kim

IPC: G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A vertical type memory device includes a first pillar structure in a channel hole inside a word line mold, and a second pillar structure in a string select line hole overlapping the channel hole inside a string select line mold. The first pillar structure includes a first gate insulating layer and a cell channel layer on an inner wall of the channel hole, a variable resistance layer on one side of the cell channel layer, a first filling insulating layer filling the channel hole, and a connection pad in an upper portion of the first filling insulating layer. The second pillar structure includes a second gate insulating layer on an inner wall of the string select line hole, a select channel layer on one side of the second gate insulating layer, and a second filling insulating layer filling the string select line hole on the select channel layer.

公开(公告)号：US20240107775A1

公开(公告)日：2024-03-28

申请号：US18368098

申请日：2023-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook Choi ,  Hyunmog Park ,  JIHONG KIM

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: An integrated circuit device includes a plurality of conductive lines on a semiconductor substrate, the plurality of conductive lines extending in a horizontal direction and overlapping each other in a vertical direction, a plurality of insulating layers alternating with the plurality of conductive lines in a vertical direction and extending in the horizontal direction, and a channel structure extending through the plurality of conductive lines and the plurality of insulating layers in the vertical direction. The channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, an information storage layer on an outside wall of the channel layer, and a pad pattern covering a top surface of the core insulating layer. The pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the information storage layer.