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    Programming memory cells using encoded TLC-fine
    3.
    发明授权
    Programming memory cells using encoded TLC-fine 有权

    公开(公告)号：US11177002B1

    公开(公告)日：2021-11-16

    申请号：US16916285

    申请日：2020-06-30

    Applicant: SanDisk Technologies LLC

    Inventor： Xue Pitner ,  Ravi Kumar ,  Deepanshu Dutta

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G06F12/02 ,  G06F12/0882 ,  G11C29/42

    Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to receive a parity bit that has been stored using a data structure, and to receive a first subset of host data that includes block data relating to a set of memory cells. The control circuitry may be configured to perform a read operation to identify a second subset of host data that includes additional block data relating to the set of memory cells. The control circuitry may be configured to decode the second subset of host data using the parity bit. The control circuitry may be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the set of memory cells.

    PROGRAM VOLTAGE DEPENDENT PROGRAM SOURCE LEVELS
    4.
    发明公开
    PROGRAM VOLTAGE DEPENDENT PROGRAM SOURCE LEVELS 审中-公开

    公开(公告)号：US20230253047A1

    公开(公告)日：2023-08-10

    申请号：US17665824

    申请日：2022-02-07

    Applicant: SanDisk Technologies LLC

    Inventor： Xue Pitner ,  Yu-Chung Lien ,  Sarath Puthenthermadam ,  Sujjatul Islam

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11556

    Abstract: A non-volatile semiconductor memory device, described herein, comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to, during a program iteration of a program operation, determine whether a program voltage level of the program iteration exceeds a threshold program voltage level and in response to the determination, identify a set of voltage levels to apply to a source line connected to a set of the non-volatile storage elements. The one or more control circuits are further configured to perform the program iteration of the program operation on the set of non-volatile storage elements, where the program iteration includes applying the set of voltage levels to the source line.

    ALL STRING VERIFY MODE FOR SINGLE-LEVEL CELL
    5.
    发明申请
    ALL STRING VERIFY MODE FOR SINGLE-LEVEL CELL 有权

    公开(公告)号：US20210327520A1

    公开(公告)日：2021-10-21

    申请号：US16854030

    申请日：2020-04-21

    Applicant: SanDisk Technologies LLC

    Inventor： Xue Pitner ,  Deepanshu Dutta ,  Huai-Yuan Tseng ,  Ravi Kumar ,  Cynthia Hsu

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08

    Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.

    Modified verify in a memory device
    6.
    发明授权
    Modified verify in a memory device 有权

    公开(公告)号：US11475967B1

    公开(公告)日：2022-10-18

    申请号：US17307626

    申请日：2021-05-04

    Applicant: SanDisk Technologies LLC

    Inventor： Xue Pitner ,  Muhammad Masuduzzaman ,  Ravi Kumar

    IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11565 ,  G11C11/56 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519

    Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.

    SELECTIVE INHIBIT BITLINE VOLTAGE TO CELLS WITH WORSE PROGRAM DISTURB
    9.
    发明公开
    SELECTIVE INHIBIT BITLINE VOLTAGE TO CELLS WITH WORSE PROGRAM DISTURB 审中-公开

    公开(公告)号：US20230274785A1

    公开(公告)日：2023-08-31

    申请号：US17682280

    申请日：2022-02-28

    Applicant: SanDisk Technologies LLC

    Inventor： Sujjatul Islam ,  Yu-Chung Lien ,  Ravi Kumar ,  Xue Pitner

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/14

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/14 ,  G11C16/26

    Abstract: A non-volatile semiconductor memory device comprises non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.

    MODIFIED VERIFY IN A MEMORY DEVICE
    10.
    发明申请
    MODIFIED VERIFY IN A MEMORY DEVICE 有权

    公开(公告)号：US20220359024A1

    公开(公告)日：2022-11-10

    申请号：US17307626

    申请日：2021-05-04

    Applicant: SanDisk Technologies LLC

    Inventor： Xue Pitner ,  Muhammad Masuduzzaman ,  Ravi Kumar

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

    Abstract: The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.

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