公开(公告)号：US08582347B2

公开(公告)日：2013-11-12

申请号：US13751592

申请日：2013-01-28

Applicant: Seagate Technology LLC

Inventor： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC: G11C11/10

CPC classification number: G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.

Abstract translation: 用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。 写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

公开(公告)号：US20130135922A1

公开(公告)日：2013-05-30

申请号：US13751592

申请日：2013-01-28

Applicant: Seagate Technology LLC

Inventor： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as an STRAM memory cell or an RRAM memory cell. In some embodiments, a plurality of N non-volatile memory cells, where N is a greater than two, are connected to a common floating source line. A write circuit is adapted to program a selected memory cell of the plurality to a selected data state by passing a write current of selected magnitude through the selected memory cell and concurrently passing a portion of the write current in parallel through each of the remaining N−1 memory cells of the plurality via the common floating source line.

Abstract translation: 用于将数据写入诸如STRAM存储器单元或RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，其中N大于2的多个N个非易失性存储器单元连接到公共的浮动源线。 写入电路适于通过将所选择的大小的写入电流通过所选择的存储器单元来编程所选择的数据状态的所选择的存储单元，并且并行地通过所述剩余的N- 1个存储单元经由公共浮动源线。

公开(公告)号：US20130302948A1

公开(公告)日：2013-11-14

申请号：US13947289

申请日：2013-07-22

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Dadi Setiadi ,  Peter Nicholas Manos ,  Hsing-Kuen Liou ,  Paramasivan Kamatchi Subramanian ,  Young Pil Kim ,  Hyung-Kyu Lee ,  Maroun Georges Khoury ,  Chulmin Jung

IPC: H01L21/8239

CPC classification number: H01L21/8239 ,  H01L21/823487 ,  H01L27/1052 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481

Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.

Abstract translation: 存储器阵列包括基本电路层和顺序堆叠以形成存储器阵列的多个存储器阵列层。 每个存储器阵列层电耦合到基极电路层。 每个存储器阵列层包括多个存储器单元。 每个存储单元包括电耦合到存储单元的垂直柱状晶体管。

公开(公告)号：US20140097400A1

公开(公告)日：2014-04-10

申请号：US14101801

申请日：2013-12-10

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Young Pil Kim ,  Hyung-Kew Lee ,  Peter Nicholas Manos ,  Chulmin Jung ,  Maroun Georges Khoury ,  Dadi Setiadi

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L27/228 ,  H01L27/2454 ,  H01L45/1206

Abstract: A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

Abstract translation: 垂直晶体管包括具有从半导体晶片正交延伸的多个柱结构的半导体晶片。 每个柱结构形成具有与顶表面正交的顶表面和侧表面的垂直柱晶体管。 然后将硬化离子物质注入垂直柱晶体管顶表面。 然后，垂直柱状晶体管侧面被氧化，形成侧面氧化层。 去除侧面氧化物层以形成具有圆形侧表面的垂直柱状晶体管。